qcs615-ride device fails to boot with qcom-6.18.y

[sgaud-quic]

qcs615-ride device fails to boot with qcom-6.18.y, with PCIE failures :

Board : qcs615-ride
Kernel : qcom-6.18.y
LAVA job : https://lava.infra.foundries.io/scheduler/job/319588

[   11.469482] pcieport 0000:00:00.0: AER: enabled with IRQ 154
[   11.469515] pcieport 0000:00:00.0: AER: Multiple Correctable error message received from 0000:01:00.0
[   11.490033] pci 0000:01:00.0: PCIe Bus Error: severity=Correctable, type=Physical Layer, (Receiver ID)
[   11.496139] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[   11.499847] pci 0000:01:00.0:   device [168c:003e] error status/mask=00000081/00006000
[   11.505716] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
[   11.513947] pci 0000:01:00.0:    [ 0] RxErr                  (First)
[[0;32m  OK  [0m] Reached target [0;1;39mHardware activated U[   11.528283] pci 0000:01:00.0:    [ 7] BadDLLP               
SB gadget[0m.
[   11.540076] pcieport 0000:00:00.0: AER: Correctable error message received from 0000:01:00.0
[   11.550283] pci 0000:01:00.0: PCIe Bus Error: severity=Correctable, type=Physical Layer, (Receiver ID)
[   11.559903] pci 0000:01:00.0:   device [168c:003e] error status/mask=00000081/00006000
[   11.568056] pci 0000:01:00.0:    [ 0] RxErr                  (First)
[   11.574611] pci 0000:01:00.0:    [ 7] BadDLLP               
[   11.580835] pcieport 0000:00:00.0: AER: Multiple Correctable error message received from 0000:01:00.0
[   11.590618] pcieport 0000:00:00.0: PCIe Bus Error: severity=Correctable, type=Data Link Layer, (Transmitter ID)
[   11.601366] pcieport 0000:00:00.0:   device [17cb:010a] error status/mask=00001000/0000e000
[   11.601422] pcieport 0000:00:00.0:    [12] Timeout               

[ziyuezhang-123]

[Talos EVK] AER Correctable Errors on QCA6174 (ROME EP, Gen1x1)
Commit f176c47 ("PCI: qcom: Advertise Hotplug Slot Capability with no Command Completion support") re-enabled the HPC bit on the Root Port, causing pciehp to load and retrain the PCIe
link. QCA6174 produces transient RxErr + BadDLLP during link retraining — these are benign physical layer noise captured by AER, not a hardware fault.
Root Cause
qcom_pcie_set_slot_nccs() uses val |= PCI_EXP_SLTCAP_NCCS (preserves HPC bit) instead of the previous val &= ~PCI_EXP_SLTCAP_HPC (cleared HPC bit). With HPC bit set, pdev->is_pciehp=1 →
pciehp loads → writes SLTCTL → triggers link retraining → AER reports correctable errors on QCA6174.
Mitigation
Mask RxErr (bit 0) in QCA6174's AER correctable error mask register, or evaluate disabling pciehp on Talos-ride.