diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml index ebb40c48950ab..3f9645fbc3c20 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml @@ -68,8 +68,8 @@ properties: - description: MPM pin number - description: GIC SPI number for the MPM pin - '#power-domain-cells': - const: 0 + power-domains: + maxItems: 1 required: - compatible @@ -113,6 +113,6 @@ examples: <24 79>, <86 183>, <91 260>; - #power-domain-cells = <0>; + power-domains = <&cluster_pd>; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index d947418302674..cc2be50a30ad6 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -202,7 +202,6 @@ cluster_pd: power-domain-cpu-cluster { #power-domain-cells = <0>; - power-domains = <&mpm>; domain-idle-states = <&cluster_sleep>; }; }; @@ -278,7 +277,6 @@ mboxes = <&apcs_glb 1>; interrupt-controller; #interrupt-cells = <2>; - #power-domain-cells = <0>; interrupt-parent = <&intc>; qcom,mpm-pin-count = <96>; qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 812ad89a649e2..bbe198d4a476e 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -3,23 +3,13 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ -#include -#include -#include #include -#include #include -#include #include -#include -#include #include #include #include #include -#include -#include -#include / { interrupt-parent = <&intc>; @@ -27,22 +17,6 @@ #address-cells = <2>; #size-cells = <2>; - bam_dmux: bam-dmux { - compatible = "qcom,bam-dmux"; - - interrupts-extended = <&modem_smsm 1 IRQ_TYPE_EDGE_BOTH>, - <&modem_smsm 11 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "pc", - "pc-ack"; - - qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; - qcom,smem-state-names = "pc", - "pc-ack"; - - dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; - dma-names = "tx", "rx"; - }; - clocks { xo_board: xo-board { compatible = "fixed-clock"; @@ -66,17 +40,11 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x0>; enable-method = "psci"; + power-domains = <&cpu_pd0>; + power-domain-names = "psci"; next-level-cache = <&l3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; - clocks = <&cpufreq_hw 0>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, - <&epss_l3 MASTER_EPSS_L3_APPS - &epss_l3 SLAVE_EPSS_L3_SHARED>; }; cpu1: cpu@100 { @@ -84,17 +52,11 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x100>; enable-method = "psci"; + power-domains = <&cpu_pd1>; + power-domain-names = "psci"; next-level-cache = <&l3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; - clocks = <&cpufreq_hw 0>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, - <&epss_l3 MASTER_EPSS_L3_APPS - &epss_l3 SLAVE_EPSS_L3_SHARED>; }; cpu2: cpu@200 { @@ -102,17 +64,11 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x200>; enable-method = "psci"; + power-domains = <&cpu_pd2>; + power-domain-names = "psci"; next-level-cache = <&l3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; - clocks = <&cpufreq_hw 0>; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, - <&epss_l3 MASTER_EPSS_L3_APPS - &epss_l3 SLAVE_EPSS_L3_SHARED>; }; cpu3: cpu@300 { @@ -120,17 +76,11 @@ compatible = "arm,cortex-a78c"; reg = <0x0 0x300>; enable-method = "psci"; + power-domains = <&cpu_pd3>; + power-domain-names = "psci"; next-level-cache = <&l2_3>; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <489>; - clocks = <&cpufreq_hw 1>; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - operating-points-v2 = <&cpu3_opp_table>; - interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, - <&epss_l3 MASTER_EPSS_L3_APPS - &epss_l3 SLAVE_EPSS_L3_SHARED>; l2_3: l2-cache { compatible = "cache"; @@ -163,6 +113,61 @@ }; }; + idle-states { + entry-method = "psci"; + + little_cpu_sleep_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-power-down"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + local-timer-stop; + }; + + little_cpu_sleep_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "little-pll-power-down"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <4001>; + local-timer-stop; + }; + + big_cpu_sleep_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-power-down"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <523>; + exit-latency-us = <1244>; + min-residency-us = <2207>; + local-timer-stop; + }; + + big_cpu_sleep_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "big-pll-power-down"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <5555>; + local-timer-stop; + }; + }; + + domain_idle_states: domain-idle-states { + cluster_sleep_apss_off: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-power-down"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3038>; + min-residency-us = <6118>; + }; + }; + l3: l3-cache { compatible = "cache"; cache-level = <3>; @@ -188,101 +193,51 @@ /* We expect the bootloader to fill in the size */ reg = <0x0 0x80000000 0x0 0x0>; }; - cpu0_opp_table: opp-table-cpu0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-768000000 { - opp-hz = /bits/ 64 <768000000>; - opp-peak-kBps = <1200000 17817600>; - }; - - opp-1017600000 { - opp-hz = /bits/ 64 <1017600000>; - opp-peak-kBps = <2188000 25804800>; - }; - - opp-1094400000 { - opp-hz = /bits/ 64 <1094400000>; - opp-peak-kBps = <3072000 30105600>; - }; - opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; - opp-peak-kBps = <4068000 38707200>; - }; - - opp-1612800000 { - opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <6220000 43008000>; - }; - - opp-1804800000 { - opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <7216000 43622400>; - }; - - opp-2208000000 { - opp-hz = /bits/ 64 <2208000000>; - opp-peak-kBps = <7216000 43622400>; - }; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; }; - cpu3_opp_table: opp-table-cpu3 { - compatible = "operating-points-v2"; - opp-shared; - - opp-768000000 { - opp-hz = /bits/ 64 <768000000>; - opp-peak-kBps = <1200000 17817600>; - }; + pmu-a78c { + compatible = "arm,cortex-a78-pmu"; + interrupts = ; + }; - opp-1017600000 { - opp-hz = /bits/ 64 <1017600000>; - opp-peak-kBps = <2188000 25804800>; - }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; - opp-1190400000 { - opp-hz = /bits/ 64 <1190400000>; - opp-peak-kBps = <3072000 30105600>; + cpu_pd0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; - opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; - opp-peak-kBps = <4068000 38707200>; + cpu_pd1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; - opp-1708800000 { - opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <6220000 43008000>; + cpu_pd2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; - opp-1900800000 { - opp-hz = /bits/ 64 <1900800000>; - opp-peak-kBps = <7216000 43622400>; + cpu_pd3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; - opp-2208000000 { - opp-hz = /bits/ 64 <2208000000>; - opp-peak-kBps = <7216000 43622400>; + cluster_pd: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&cluster_sleep_apss_off>; }; }; - pmu-a55 { - compatible = "arm,cortex-a55-pmu"; - interrupts = ; - }; - - pmu-a78c { - compatible = "arm,cortex-a78-pmu"; - interrupts = ; - }; - - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - rpm: remoteproc { compatible = "qcom,shikra-rpm-proc", "qcom,rpm-proc"; @@ -297,7 +252,7 @@ qcom,glink-channels = "rpm_requests"; rpmcc: clock-controller { - compatible = "qcom,rpmcc-shikra", "qcom,rpmcc"; + compatible = "qcom,rpmcc-shikra", "qcom,rpmcc-qcm2290", "qcom,rpmcc"; clocks = <&xo_board>; clock-names = "xo"; #clock-cells = <1>; @@ -354,8 +309,8 @@ mboxes = <&apcs_glb 1>; interrupt-controller; #interrupt-cells = <2>; - #power-domain-cells = <0>; interrupt-parent = <&intc>; + power-domains = <&cluster_pd>; qcom,mpm-pin-count = <96>; qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ <12 422>, /* DWC3 ss_phy_irq */ @@ -396,14 +351,7 @@ }; audio_heap_mem: audio-heap@86200000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x86200000 0x0 0x40000>; - no-map; - }; - - audio_mdsp_carveout_mem: audio-mdsp-carveout@86240000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x86240000 0x0 0x100000>; + reg = <0x0 0x86200000 0x0 0x100000>; no-map; }; @@ -458,97 +406,6 @@ }; }; - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - - interrupts = ; - - mboxes = <&apcs_glb 6>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - cdsp_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - cdsp_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-lmcu { - compatible = "qcom,smp2p"; - qcom,smem = <617>, <616>; - - interrupts = ; - - mboxes = <&apcs_glb 10>; - - qcom,local-pid = <0>; - qcom,remote-pid = <26>; - - lmcu_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - lmcu_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-mpss { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - - interrupts = ; - - mboxes = <&apcs_glb 14>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - modem_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - modem_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smsm { - compatible = "qcom,smsm"; - - #address-cells = <1>; - #size-cells = <0>; - - mboxes = <0>, <&apcs_glb 13>; - - apps_smsm: apps@0 { - reg = <0>; - #qcom,smem-state-cells = <1>; - }; - - modem_smsm: modem@1 { - reg = <1>; - interrupts = ; - - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - soc: soc@0 { compatible = "simple-bus"; @@ -583,221 +440,6 @@ gpio-ranges = <&tlmm 0 0 165>; wakeup-parent = <&mpm>; - cci_i2c0_default: cci-i2c0-default-state { - /* SDA, SCL */ - pins = "gpio36", "gpio37"; - function = "cci_i2c0"; - drive-strength = <2>; - bias-pull-up; - }; - - cci_i2c0_sleep: cci-i2c0-sleep-state { - /* SDA, SCL */ - pins = "gpio36", "gpio37"; - function = "cci_i2c0"; - drive-strength = <2>; - bias-pull-down; - }; - - cci_i2c1_default: cci-i2c1-default-state { - /* SDA, SCL */ - pins = "gpio41", "gpio42"; - function = "cci_i2c1"; - drive-strength = <2>; - bias-pull-up; - }; - - cci_i2c1_sleep: cci-i2c1-sleep-state { - /* SDA, SCL */ - pins = "gpio41", "gpio42"; - function = "cci_i2c1"; - drive-strength = <2>; - bias-pull-down; - }; - - mclk0_default: mclk0-default-state { - pins = "gpio34"; - function = "cam_mclk"; - drive-strength = <2>; - bias-disable; - }; - - mclk1_default: mclk1-default-state { - pins = "gpio35"; - function = "cam_mclk"; - drive-strength = <2>; - bias-disable; - }; - - mclk2_default: mclk2-default-state { - pins = "gpio96"; - function = "cam_mclk"; - drive-strength = <2>; - bias-disable; - }; - - mclk3_default: mclk3-default-state { - pins = "gpio98"; - function = "cam_mclk"; - drive-strength = <2>; - bias-disable; - }; - - qup_i2c0_data_clk: qup-i2c0-data-clk-state { - /* SDA, SCL */ - pins = "gpio2", "gpio3"; - function = "qup0_se0"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c1_data_clk: qup-i2c1-data-clk-state { - /* SDA, SCL */ - pins = "gpio4", "gpio5"; - function = "qup0_se1_01"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c2_data_clk: qup-i2c2-data-clk-state { - /* SDA, SCL */ - pins = "gpio6", "gpio7"; - function = "qup0_se2"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c3_data_clk: qup-i2c3-data-clk-state { - /* SDA, SCL */ - pins = "gpio10", "gpio11"; - function = "qup0_se3_01"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c4_data_clk: qup-i2c4-data-clk-state { - /* SDA, SCL */ - pins = "gpio12", "gpio13"; - function = "qup0_se4_01"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c5_data_clk: qup-i2c5-data-clk-state { - /* SDA, SCL */ - pins = "gpio14", "gpio15"; - function = "qup0_se5"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c6_data_clk: qup-i2c6-data-clk-state { - /* SDA, SCL */ - pins = "gpio18", "gpio19"; - function = "qup0_se6"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c7_data_clk: qup-i2c7-data-clk-state { - /* SDA, SCL */ - pins = "gpio20", "gpio21"; - function = "qup0_se7_01"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c8_data_clk: qup-i2c8-data-clk-state { - /* SDA, SCL */ - pins = "gpio22", "gpio23"; - function = "qup0_se8"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c9_data_clk: qup-i2c9-data-clk-state { - /* SDA, SCL */ - pins = "gpio27", "gpio26"; - function = "qup0_se9_01"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_spi0_cs: qup-spi0-cs-state { - pins = "gpio1"; - function = "qup0_se0"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi0_data_clk: qup-spi0-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio2", "gpio3", "gpio0"; - function = "qup0_se0"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi2_cs: qup-spi2-cs-state { - pins = "gpio9"; - function = "qup0_se2"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi2_data_clk: qup-spi2-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio6", "gpio7", "gpio8"; - function = "qup0_se2"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi5_cs: qup-spi5-cs-state { - pins = "gpio17"; - function = "qup0_se5"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi5_data_clk: qup-spi5-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio14", "gpio15", "gpio16"; - function = "qup0_se5"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi6_cs: qup-spi6-cs-state { - pins = "gpio29"; - function = "qup0_se6"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi6_data_clk: qup-spi6-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio18", "gpio19", "gpio28"; - function = "qup0_se6"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi8_cs: qup-spi8-cs-state { - pins = "gpio25"; - function = "qup0_se8"; - drive-strength = <6>; - bias-disable; - }; - - qup_spi8_data_clk: qup-spi8-data-clk-state { - /* MISO, MOSI, CLK */ - pins = "gpio22", "gpio23", "gpio24"; - function = "qup0_se8"; - drive-strength = <6>; - bias-disable; - }; - qup_uart0_default: qup-uart0-default-state { pins = "gpio0", "gpio1"; function = "qup0_se0"; @@ -805,105 +447,6 @@ bias-disable; }; - qup_uart1_default: qup-uart1-default-state { - pins = "gpio4", "gpio5"; - function = "qup0_se1_23"; - drive-strength = <2>; - bias-disable; - }; - - qup_uart2_default: qup-uart2-default-state { - /* TX, RX */ - pins = "gpio8", "gpio9"; - function = "qup0_se2"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_uart2_cts_rts: qup-uart2-cts-rts-state { - /* CTS, RTS */ - pins = "gpio6", "gpio7"; - function = "qup0_se2"; - drive-strength = <2>; - bias-pull-down; - }; - - qup_uart3_default: qup-uart3-default-state { - pins = "gpio10", "gpio11"; - function = "qup0_se3_23"; - drive-strength = <2>; - bias-disable; - }; - - qup_uart4_default: qup-uart4-default-state { - pins = "gpio12", "gpio13"; - function = "qup0_se4_23"; - drive-strength = <2>; - bias-disable; - }; - - qup_uart5_default: qup-uart5-default-state { - /* TX, RX */ - pins = "gpio16", "gpio17"; - function = "qup0_se5"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_uart5_cts_rts: qup-uart5-cts-rts-state { - /* CTS, RTS */ - pins = "gpio14", "gpio15"; - function = "qup0_se5"; - drive-strength = <2>; - bias-pull-down; - }; - - qup_uart6_default: qup-uart6-default-state { - /* TX, RX */ - pins = "gpio28", "gpio29"; - function = "qup0_se6"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_uart6_cts_rts: qup-uart6-cts-rts-state { - /* CTS, RTS */ - pins = "gpio18", "gpio19"; - function = "qup0_se6"; - drive-strength = <2>; - bias-pull-down; - }; - - qup_uart7_default: qup-uart7-default-state { - pins = "gpio20", "gpio21"; - function = "qup0_se7_23"; - drive-strength = <2>; - bias-disable; - }; - - qup_uart8_default: qup-uart8-default-state { - /* TX, RX */ - pins = "gpio24", "gpio25"; - function = "qup0_se8"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_uart8_cts_rts: qup-uart8-cts-rts-state { - /* CTS, RTS */ - pins = "gpio22", "gpio23"; - function = "qup0_se8"; - drive-strength = <2>; - bias-pull-down; - }; - - qup_uart9_default: qup-uart9-default-state { - pins = "gpio26", "gpio27"; - function = "qup0_se9_23"; - drive-strength = <2>; - bias-disable; - }; - sdc1_state_on: sdc1-on-state { clk-pins { pins = "sdc1_clk"; @@ -953,158 +496,7 @@ bias-bus-hold; }; }; - - sdc2_default: sdc2-default-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <14>; - bias-disable; - }; - - cmd-pins { - pins = "sdc2_cmd"; - drive-strength = <14>; - bias-pull-up; - }; - - data-pins { - pins = "sdc2_data"; - drive-strength = <14>; - bias-pull-up; - }; - }; - - sdc2_sleep: sdc2-sleep-state { - clk-pins { - pins = "sdc2_clk"; - drive-strength = <2>; - bias-disable; - }; - - cmd-pins { - pins = "sdc2_cmd"; - drive-strength = <2>; - bias-pull-up; - }; - - data-pins { - pins = "sdc2_data"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - sdc2_card_det_n: sd-card-det-n-state { - pins = "gpio89"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - dmic01_default: dmic01-default-state { - clk-pins { - pins = "gpio96"; - function = "dmic"; - drive-strength = <8>; - output-high; - }; - - data-pins { - pins = "gpio97"; - function = "dmic"; - drive-strength = <8>; - bias-disable; - }; - }; - - dmic23_default: dmic23-default-state { - clk-pins { - pins = "gpio98"; - function = "dmic"; - drive-strength = <8>; - output-high; - }; - - data-pins { - pins = "gpio99"; - function = "dmic"; - drive-strength = <8>; - bias-disable; - }; - }; - - tx_swr_active: tx-swr-active-state { - clk-pins { - pins = "gpio105"; - function = "swr0_tx"; - drive-strength = <8>; - bias-disable; - }; - - data-pins { - pins = "gpio106"; - function = "swr0_tx"; - drive-strength = <8>; - bias-bus-hold; - }; - }; - - rx_swr_active: rx-swr-active-state { - clk-pins { - pins = "gpio107"; - function = "swr0_rx"; - drive-strength = <8>; - bias-disable; - }; - - data-pins { - pins = "gpio108", "gpio109"; - function = "swr0_rx"; - drive-strength = <8>; - bias-bus-hold; - }; - }; - }; - - pmu@c91000 { - compatible = "qcom,shikra-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; - reg = <0x0 0x00c91000 0x0 0x1000>; - - interrupts = ; - - interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>; - - operating-points-v2 = <&cpu_bwmon_opp_table>; - - cpu_bwmon_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-0 { - opp-peak-kBps = <1200000>; - }; - - opp-1 { - opp-peak-kBps = <2188000>; - }; - - opp-2 { - opp-peak-kBps = <3072000>; - }; - - opp-3 { - opp-peak-kBps = <4068000>; - }; - - opp-4 { - opp-peak-kBps = <6220000>; - }; - - opp-5 { - opp-peak-kBps = <7216000>; - }; - }; - }; + }; mem_noc: interconnect@d00000 { compatible = "qcom,shikra-mem-noc-core"; @@ -1142,70 +534,6 @@ #power-domain-cells = <1>; }; - usb_1_hsphy: phy@1613000 { - compatible = "qcom,shikra-qusb2-phy"; - reg = <0x0 0x01613000 0x0 0x180>; - - clocks = <&gcc GCC_AHB2PHY_USB_CLK>, - <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - nvmem-cells = <&qusb2_hstx_trim_1>; - #phy-cells = <0>; - - status = "disabled"; - }; - - usb_qmpphy: phy@1615000 { - compatible = "qcom,shikra-qmp-usb3-phy"; - reg = <0x0 0x01615000 0x0 0x1000>; - - clocks = <&gcc GCC_AHB2PHY_USB_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_EN>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "cfg_ahb", - "ref", - "com_aux", - "pipe"; - - resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, - <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; - reset-names = "phy", - "phy_phy"; - - #clock-cells = <0>; - clock-output-names = "usb3_phy_pipe_clk_src"; - - #phy-cells = <0>; - orientation-switch; - - qcom,tcsr-reg = <&tcsr_regs 0xb244>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_qmpphy_out: endpoint { - }; - }; - - port@1 { - reg = <1>; - - usb_qmpphy_usb_ss_in: endpoint { - remote-endpoint = <&usb_1_dwc3_ss>; - }; - }; - }; - }; - system_noc: interconnect@1880000 { compatible = "qcom,shikra-sys-noc"; reg = <0x0 0x01880000 0x0 0x6a080>; @@ -1246,41 +574,6 @@ #interconnect-cells = <2>; }; - cryptobam: dma-controller@1b04000 { - compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; - reg = <0x0 0x01b04000 0x0 0x24000>; - interrupts = ; - #dma-cells = <1>; - iommus = <&apps_smmu 0x84 0x0011>, - <&apps_smmu 0x86 0x0011>, - <&apps_smmu 0x92 0x0>, - <&apps_smmu 0x94 0x0011>, - <&apps_smmu 0x96 0x0011>, - <&apps_smmu 0x98 0x0001>, - <&apps_smmu 0x9f 0x0>; - qcom,ee = <0>; - qcom,controlled-remotely; - num-channels = <16>; - qcom,num-ees = <4>; - }; - - crypto: crypto@1b3a000 { - compatible = "qcom,shikra-qce", "qcom,sm8150-qce", "qcom,qce"; - reg = <0x0 0x01b3a000 0x0 0x6000>; - dmas = <&cryptobam 4>, <&cryptobam 5>; - dma-names = "rx", "tx"; - iommus = <&apps_smmu 0x84 0x0011>, - <&apps_smmu 0x86 0x0011>, - <&apps_smmu 0x92 0x0>, - <&apps_smmu 0x94 0x0011>, - <&apps_smmu 0x96 0x0011>, - <&apps_smmu 0x98 0x0001>, - <&apps_smmu 0x9f 0x0>; - interconnects = <&system_noc MASTER_CRYPTO_CORE0 0 - &mc_virt SLAVE_EBI_CH0 0>; - interconnect-names = "memory"; - }; - qfprom: efuse@1b44000 { compatible = "qcom,shikra-qfprom", "qcom,qfprom"; reg = <0x0 0x01b44000 0x0 0x3000>; @@ -1320,189 +613,13 @@ qcom,ee = <0>; }; - rng: rng@4454000 { - compatible = "qcom,shikra-trng", "qcom,trng"; - reg = <0x0 0x04454000 0x0 0x1000>; - }; - - tsens0: thermal-sensor@4411000 { - compatible = "qcom,shikra-tsens", "qcom,tsens-v2"; - reg = <0x0 0x04411000 0x0 0x1000>, - <0x0 0x04410000 0x0 0x1000>; - interrupts = , - ; - interrupt-names = "uplow", - "critical"; - #qcom,sensors = <14>; - #thermal-sensor-cells = <1>; - }; - - pcie: pcie@45e8000 { - device_type = "pci"; - compatible = "qcom,pcie-shikra"; - reg = <0x0 0x045e8000 0x0 0x3000>, - <0x0 0x60000000 0x0 0xf1d>, - <0x0 0x60000f20 0x0 0xa8>, - <0x0 0x60001000 0x0 0x1000>, - <0x0 0x60100000 0x0 0x100000>, - <0x0 0x045eb000 0x0 0x1000>; - reg-names = "parf", - "dbi", - "elbi", - "atu", - "config", - "mhi"; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; - bus-range = <0x00 0xff>; - - linux,pci-domain = <0>; - num-lanes = <1>; - - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "msi0", - "msi1", - "msi2", - "msi3", - "msi4", - "msi5", - "msi6", - "msi7", - "global"; - - interrupt-map = <0 0 0 1 &intc 0 0 0 499 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc 0 0 0 500 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc 0 0 0 501 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc 0 0 0 502 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0 0 0 0x7>; - #interrupt-cells = <1>; - - clocks = <&gcc GCC_PCIE_AUX_CLK>, - <&gcc GCC_PCIE_CFG_AHB_CLK>, - <&gcc GCC_PCIE_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_SLV_AXI_CLK>, - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_SLEEP_CLK>, - <&gcc GCC_PCIE_THROTTLE_CORE_CLK>, - <&gcc GCC_PCIE_THROTTLE_XO_CLK>, - <&gcc GCC_QMIP_PCIE_CFG_AHB_CLK>, - <&gcc GCC_DDRSS_MEMNOC_PCIE_SF_CLK>, - <&gcc GCC_PCIE_TILE_AXI_SYS_NOC_CLK>; - - clock-names = "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "sleep", - "throttle_core", - "throttle_xo", - "qmip", - "ddrss", - "tile"; - assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>; - assigned-clock-rates = <19200000>; - - interconnects = <&system_noc MASTER_PCIE2_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, - <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_PCIE2_0 QCOM_ICC_TAG_ACTIVE_ONLY>; - - interconnect-names = "pcie-mem", - "cpu-pcie"; - - iommu-map = <0x0 &apps_smmu 0x800 0x1>, - <0x100 &apps_smmu 0x801 0x1>; - - resets = <&gcc GCC_PCIE_BCR>; - reset-names = "pci"; - - power-domains = <&gcc GCC_PCIE_GDSC>; - - max-link-speed = <2>; - - operating-points-v2 = <&pcie_opp_table>; - - status = "disabled"; - - pcie_opp_table: opp-table { - compatible = "operating-points-v2"; - - /* GEN 1 x1 */ - opp-2500000 { - opp-hz = /bits/ 64 <2500000>; - required-opps = <&rpmpd_opp_nom>; - opp-peak-kBps = <250000 1>; - opp-level = <1>; - }; - - /* GEN 2 x1 */ - opp-5000000 { - opp-hz = /bits/ 64 <5000000>; - required-opps = <&rpmpd_opp_nom>; - opp-peak-kBps = <500000 1>; - opp-level = <2>; - }; - }; - - pcie_port0: pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - bus-range = <0x01 0x8>; - - phys = <&pcie_phy>; - }; - }; - - pcie_phy: phy@45ee000 { - compatible = "qcom,shikra-qmp-gen2x1-pcie-phy"; - reg = <0x0 0x045ee000 0x0 0x1000>; - - clocks = <&gcc GCC_PCIE_AUX_CLK>, - <&gcc GCC_PCIE_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_EN>, - <&gcc GCC_PCIE_RCHNG_PHY_CLK>, - <&gcc GCC_PCIE_PIPE_CLK>; - clock-names = "aux", - "cfg_ahb", - "ref", - "refgen", - "pipe"; - - resets = <&gcc GCC_PCIE_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; - assigned-clock-rates = <100000000>; - - #clock-cells = <0>; - clock-output-names = "pcie_pipe_clk"; - - #phy-cells = <0>; - - status = "disabled"; - }; - rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram", "mmio-sram"; reg = <0x0 0x045f0000 0x0 0x7000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x0 0x045f0000 0x7000>; + ranges = <0x0 0x0 0x045f0000 0x7000>; apss_mpm: sram@1b8 { reg = <0x1b8 0x48>; @@ -1537,9 +654,9 @@ "xo"; interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG - &config_noc SLAVE_SDCC_1 RPM_ACTIVE_TAG>; + &config_noc SLAVE_SDCC_1 RPM_ACTIVE_TAG>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; @@ -1557,7 +674,6 @@ mmc-hs400-enhanced-strobe; resets = <&gcc GCC_SDCC1_BCR>; - qcom,ice = <&sdhc_ice>; status = "disabled"; @@ -1580,227 +696,6 @@ }; }; - sdhc_2: mmc@4784000 { - compatible = "qcom,shikra-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x0 0x4784000 0x0 0x1000>; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - bus-width = <4>; - - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "iface", "core", "xo"; - - qcom,dll-config = <0x0007442c>; - qcom,ddr-config = <0x80040868>; - - iommus = <&apps_smmu 0x0a0 0x0>; - - interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG - &config_noc SLAVE_SDCC_2 RPM_ACTIVE_TAG>; - interconnect-names = "sdhc-ddr","cpu-sdhc"; - - power-domains = <&rpmpd RPMPD_VDDCX>; - operating-points-v2 = <&sdhc2_opp_table>; - - status = "disabled"; - - sdhc2_opp_table: opp-table-2 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmpd_opp_low_svs>; - }; - - opp-202000000 { - opp-hz = /bits/ 64 <202000000>; - required-opps = <&rpmpd_opp_svs_plus>; - }; - }; - }; - - camss: camss@5c11000 { - compatible = "qcom,shikra-camss"; - - reg = <0x0 0x05c11000 0x0 0x1000>, - <0x0 0x05c6e000 0x0 0x1000>, - <0x0 0x05c75000 0x0 0x1000>, - <0x0 0x05c52000 0x0 0x1000>, - <0x0 0x05c53000 0x0 0x1000>, - <0x0 0x05c66000 0x0 0x400>, - <0x0 0x05c68000 0x0 0x400>, - <0x0 0x05c6f000 0x0 0x4000>, - <0x0 0x05c76000 0x0 0x4000>; - reg-names = "top", - "csid0", - "csid1", - "csiphy0", - "csiphy1", - "csitpg0", - "csitpg1", - "vfe0", - "vfe1"; - - clocks = <&gcc GCC_CAMERA_AHB_CLK>, - <&gcc GCC_CAMSS_AXI_CLK>, - <&gcc GCC_CAMSS_NRT_AXI_CLK>, - <&gcc GCC_CAMSS_RT_AXI_CLK>, - <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, - <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, - <&gcc GCC_CAMSS_CPHY_0_CLK>, - <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, - <&gcc GCC_CAMSS_CPHY_1_CLK>, - <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, - <&gcc GCC_CAMSS_TOP_AHB_CLK>, - <&gcc GCC_CAMSS_TFE_0_CLK>, - <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, - <&gcc GCC_CAMSS_TFE_1_CLK>, - <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>; - clock-names = "ahb", - "axi", - "camnoc_nrt_axi", - "camnoc_rt_axi", - "csi0", - "csi1", - "csiphy0", - "csiphy0_timer", - "csiphy1", - "csiphy1_timer", - "top_ahb", - "vfe0", - "vfe0_cphy_rx", - "vfe1", - "vfe1_cphy_rx"; - - interrupts = , - , - , - , - , - , - , - ; - interrupt-names = "csid0", - "csid1", - "csiphy0", - "csiphy1", - "csitpg0", - "csitpg1", - "vfe0", - "vfe1"; - - interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG - &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>, - <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, - <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; - interconnect-names = "ahb", - "hf_mnoc", - "sf_mnoc"; - - iommus = <&apps_smmu 0x400 0x0>; - power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - }; - }; - }; - - cci: cci@5c1b000 { - compatible = "qcom,shikra-cci", "qcom,msm8996-cci"; - reg = <0x0 0x05c1b000 0x0 0x1000>; - - interrupts = ; - - clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, - <&gcc GCC_CAMSS_CCI_0_CLK>; - clock-names = "ahb", - "cci"; - - power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; - - pinctrl-0 = <&cci_i2c0_default &cci_i2c1_default>; - pinctrl-1 = <&cci_i2c0_sleep &cci_i2c1_sleep>; - pinctrl-names = "default", "sleep"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - - cci_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci_i2c1: i2c-bus@1 { - reg = <1>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - sdhc_ice: crypto@4748000 { - compatible = "qcom,shikra-inline-crypto-engine", - "qcom,inline-crypto-engine"; - reg = <0x0 0x04748000 0x0 0x18000>; - clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", - "iface"; - power-domains = <&rpmpd RPMHPD_CX>; - }; - - gpi_dma0: dma-controller@4a00000 { - compatible = "qcom,shikra-gpi-dma", "qcom,sm6350-gpi-dma"; - reg = <0x0 0x04a00000 0x0 0x60000>; - - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - - dma-channels = <16>; - dma-channel-mask = <0xff>; - #dma-cells = <3>; - - iommus = <&apps_smmu 0xf6 0x0>; - }; - qupv3_0: geniqup@4ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x04ac0000 0x0 0x2000>; @@ -1810,75 +705,10 @@ clock-names = "m-ahb", "s-ahb"; - iommus = <&apps_smmu 0xe3 0x0>; - #address-cells = <2>; #size-cells = <2>; ranges; - status = "disabled"; - - i2c0: i2c@4a80000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x4a80000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, - <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - - dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, - <&gpi_dma0 1 0 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - - pinctrl-0 = <&qup_i2c0_data_clk>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi0: spi@4a80000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x4a80000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config"; - - dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, - <&gpi_dma0 1 0 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - - pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - uart0: serial@4a80000 { compatible = "qcom,geni-debug-uart"; reg = <0x0 0x04a80000 0x0 0x4000>; @@ -1900,1585 +730,17 @@ status = "disabled"; }; + }; - i2c1: i2c@4a84000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x4a84000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - clock-names = "se"; + sram@c11e000 { + compatible = "qcom,shikra-imem", "mmio-sram"; + reg = <0x0 0x0c11e000 0x0 0x1000>; + ranges = <0x0 0x0 0x0c11e000 0x1000>; - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, - <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; + no-memory-wc; - dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, - <&gpi_dma0 1 1 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - - pinctrl-0 = <&qup_i2c1_data_clk>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - uart1: serial@4a84000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x04a84000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config"; - - pinctrl-0 = <&qup_uart1_default>; - pinctrl-names = "default"; - - status = "disabled"; - }; - - i2c2: i2c@4a88000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x4a88000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, - <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - - pinctrl-0 = <&qup_i2c2_data_clk>; - pinctrl-names = "default"; - - dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, - <&gpi_dma0 1 2 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi2: spi@4a88000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x4a88000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config"; - - dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, - <&gpi_dma0 1 2 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - - pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - uart2: serial@4a88000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x04a88000 0x0 0x4000>; - - interrupts-extended = <&intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>, - <&tlmm 9 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config"; - - pinctrl-0 = <&qup_uart2_default>, <&qup_uart2_cts_rts>; - pinctrl-names = "default"; - - status = "disabled"; - }; - - i2c3: i2c@4a8c000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x4a8c000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, - <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - - dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, - <&gpi_dma0 1 3 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - - pinctrl-0 = <&qup_i2c3_data_clk>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - uart3: serial@4a8c000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x04a8c000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config"; - - pinctrl-0 = <&qup_uart3_default>; - pinctrl-names = "default"; - - status = "disabled"; - }; - - i2c4: i2c@4a90000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x4a90000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, - <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - - dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, - <&gpi_dma0 1 4 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - - pinctrl-0 = <&qup_i2c4_data_clk>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - uart4: serial@4a90000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x04a90000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config"; - - pinctrl-0 = <&qup_uart4_default>; - pinctrl-names = "default"; - - status = "disabled"; - }; - - i2c5: i2c@4a94000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x4a94000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, - <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - - dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, - <&gpi_dma0 1 5 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - - pinctrl-0 = <&qup_i2c5_data_clk>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi5: spi@4a94000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x4a94000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config"; - - dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, - <&gpi_dma0 1 5 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - - pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - uart5: serial@4a94000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x04a94000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config"; - - pinctrl-0 = <&qup_uart5_default>, <&qup_uart5_cts_rts>; - pinctrl-names = "default"; - - status = "disabled"; - }; - - i2c6: i2c@4a98000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x4a98000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, - <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - - dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, - <&gpi_dma0 1 6 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - - pinctrl-0 = <&qup_i2c6_data_clk>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi6: spi@4a98000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x4a98000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config"; - - dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, - <&gpi_dma0 1 6 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - - pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - uart6: serial@4a98000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x04a98000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config"; - - pinctrl-0 = <&qup_uart6_default>, <&qup_uart6_cts_rts>; - pinctrl-names = "default"; - - status = "disabled"; - }; - - i2c7: i2c@4a9c000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x4a9c000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, - <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - - dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, - <&gpi_dma0 1 7 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - - pinctrl-0 = <&qup_i2c7_data_clk>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - uart7: serial@4a9c000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x04a9c000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config"; - - pinctrl-0 = <&qup_uart7_default>; - pinctrl-names = "default"; - - status = "disabled"; - }; - - i2c8: i2c@4aa0000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x4aa0000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, - <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - - dmas = <&gpi_dma0 0 8 QCOM_GPI_I2C>, - <&gpi_dma0 1 8 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - - pinctrl-0 = <&qup_i2c8_data_clk>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - spi8: spi@4aa0000 { - compatible = "qcom,geni-spi"; - reg = <0x0 0x4aa0000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config"; - - dmas = <&gpi_dma0 0 8 QCOM_GPI_SPI>, - <&gpi_dma0 1 8 QCOM_GPI_SPI>; - dma-names = "tx", "rx"; - - pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - uart8: serial@4aa0000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x04aa0000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config"; - - pinctrl-0 = <&qup_uart8_default>, <&qup_uart8_cts_rts>; - pinctrl-names = "default"; - - status = "disabled"; - - bluetooth { - compatible = "qcom,wcn3988-bt"; - enable-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; - max-speed = <3200000>; - }; - - }; - - i2c9: i2c@4aa4000 { - compatible = "qcom,geni-i2c"; - reg = <0x0 0x4aa4000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, - <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config", - "qup-memory"; - - dmas = <&gpi_dma0 0 9 QCOM_GPI_I2C>, - <&gpi_dma0 1 9 QCOM_GPI_I2C>; - dma-names = "tx", "rx"; - - pinctrl-0 = <&qup_i2c9_data_clk>; - pinctrl-names = "default"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - uart9: serial@4aa4000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x04aa4000 0x0 0x4000>; - - interrupts = ; - - clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>; - clock-names = "se"; - - interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG - &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; - interconnect-names = "qup-core", - "qup-config"; - - pinctrl-0 = <&qup_uart9_default>; - pinctrl-names = "default"; - - status = "disabled"; - }; - }; - - usb_1: usb@4e00000 { - compatible = "qcom,shikra-dwc3", "qcom,snps-dwc3"; - reg = <0x0 0x04e00000 0x0 0xfc100>; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_EN>; - clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi", - "xo"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <133333333>; - - interrupts-extended = <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>, - <&intc GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>; - interrupt-names = "dwc_usb3", - "pwr_event", - "qusb2_phy", - "hs_phy_irq", - "ss_phy_irq"; - - iommus = <&apps_smmu 0x120 0x0>; - - phys = <&usb_1_hsphy>, <&usb_qmpphy>; - phy-names = "usb2-phy", "usb3-phy"; - - power-domains = <&gcc GCC_USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,has-lpm-erratum; - snps,hird-threshold = /bits/ 8 <0x10>; - snps,usb3_lpm_capable; - snps,parkmode-disable-ss-quirk; - - usb-role-switch; - - wakeup-source; - - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_1_dwc3_hs: endpoint { - }; - }; - - port@1 { - reg = <1>; - - usb_1_dwc3_ss: endpoint { - remote-endpoint = <&usb_qmpphy_usb_ss_in>; - }; - }; - }; - }; - - bam_dmux_dma: dma-controller@6044000 { - compatible = "qcom,bam-v1.7.0"; - reg = <0x0 0x06044000 0x0 0x19000>; - interrupts = ; - #dma-cells = <1>; - qcom,ee = <0>; - - num-channels = <6>; - qcom,num-ees = <1>; - qcom,powered-remotely; - }; - - remoteproc_mpss: remoteproc@6080000 { - compatible = "qcom,shikra-mpss-pas"; - reg = <0x0 0x06080000 0x0 0x100>; - - interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING 0>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", - "fatal", - "ready", - "handover", - "stop-ack", - "shutdown-ack"; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "xo"; - - interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; - - power-domains = <&rpmpd RPMHPD_CX>; - - memory-region = <&mpss_wlan_mem>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - mboxes = <&apcs_glb 12>; - qcom,remote-pid = <1>; - label = "mpss"; - - gpr: gpr { - compatible = "qcom,gpr"; - qcom,glink-channels = "modem_apps"; - qcom,domain = ; - qcom,intents = <200 20>; - #address-cells = <1>; - #size-cells = <0>; - - q6apm: service@1 { - compatible = "qcom,q6apm"; - reg = ; - #sound-dai-cells = <0>; - - q6apmbedai: bedais { - compatible = "qcom,q6apm-lpass-dais"; - #sound-dai-cells = <1>; - }; - - q6apmdai: dais { - compatible = "qcom,q6apm-dais"; - memory-region = <&audio_heap_mem - &audio_mdsp_carveout_mem>; - qcom,vmid = ; - }; - }; - - q6prm: service@2 { - compatible = "qcom,q6prm"; - reg = ; - - q6prmcc: clock-controller { - compatible = "qcom,q6prm-lpass-clocks"; - #clock-cells = <2>; - }; - }; - }; - }; - }; - - remoteproc_cdsp: remoteproc@b300000 { - compatible = "qcom,shikra-cdsp-pas"; - reg = <0x0 0x0b300000 0x0 0x100000>; - - interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING 0>, - <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, - <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", - "fatal", - "ready", - "handover", - "stop-ack", - "shutdown-ack"; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "xo"; - - interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; - - power-domains = <&rpmpd RPMHPD_CX>; - - memory-region = <&cdsp_mem>; - - qcom,smem-states = <&cdsp_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - mboxes = <&apcs_glb 4>; - qcom,remote-pid = <5>; - label = "cdsp"; - - fastrpc { - compatible = "qcom,fastrpc"; - #address-cells = <1>; - #size-cells = <0>; - label = "cdsp"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x0201 0x0000>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x0202 0x0000>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x0203 0x0000>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x0204 0x0000>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x0205 0x0000>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x0206 0x0000>; - }; - - compute-cb@9 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <9>; - iommus = <&apps_smmu 0x0209 0x0000>; - }; - }; - }; - }; - - remoteproc_lpaicp: remoteproc@b800000 { - compatible = "qcom,shikra-lpaicp-pas"; - reg = <0x0 0x0b800000 0x0 0x200000>; - - interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING 0>, - <&lmcu_smp2p_in 0 IRQ_TYPE_NONE>, - <&lmcu_smp2p_in 1 IRQ_TYPE_NONE>, - <&lmcu_smp2p_in 2 IRQ_TYPE_NONE>, - <&lmcu_smp2p_in 3 IRQ_TYPE_NONE>; - - interrupt-names = "wdog", - "fatal", - "ready", - "handover", - "stop-ack"; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "xo"; - - memory-region = <&lmcu_mem &lmcu_dtb_mem>; - - qcom,smem-states = <&lmcu_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts = ; - mboxes = <&apcs_glb 9>; - qcom,remote-pid = <26>; - label = "lpaicp"; - }; - }; - - gpu: gpu@5900000 { - compatible = "qcom,adreno-07000400", "qcom,adreno"; - reg = <0x0 0x05900000 0x0 0x40000>, - <0x0 0x0599e000 0x0 0x1000>, - <0x0 0x05961000 0x0 0x800>; - reg-names = "kgsl_3d0_reg_memory", - "cx_mem", - "cx_dbgc"; - - interrupts = ; - - clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, - <&gpucc GPU_CC_AHB_CLK>, - <&gcc GCC_DDRSS_GPU_AXI_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gpucc GPU_CC_CX_GMU_CLK>, - <&gpucc GPU_CC_CXO_CLK>; - clock-names = "core", - "iface", - "mem_iface", - "alt_mem_iface", - "gmu", - "xo"; - - interconnects = <&mem_noc MASTER_GRAPHICS_3D RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; - interconnect-names = "gfx-mem"; - - iommus = <&adreno_smmu 0 1>; - operating-points-v2 = <&gpu_opp_table>; - power-domains = <&rpmpd QCM2290_VDDCX>; - qcom,gmu = <&gmu_wrapper>; - - #cooling-cells = <2>; - - status = "disabled"; - - gpu_zap_shader: zap-shader { - memory-region = <&gpu_micro_code_mem>; - }; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-1142400000 { - opp-hz = /bits/ 64 <1142400000>; - required-opps = <&rpmpd_opp_turbo_plus>; - opp-peak-kBps = <8171875>; - }; - - opp-1017600000 { - opp-hz = /bits/ 64 <1017600000>; - required-opps = <&rpmpd_opp_turbo>; - opp-peak-kBps = <8171875>; - }; - - opp-921600000 { - opp-hz = /bits/ 64 <921600000>; - required-opps = <&rpmpd_opp_nom_plus>; - opp-peak-kBps = <7046875>; - }; - - opp-844800000 { - opp-hz = /bits/ 64 <844800000>; - required-opps = <&rpmpd_opp_nom>; - opp-peak-kBps = <6074218>; - }; - - opp-672000000 { - opp-hz = /bits/ 64 <672000000>; - required-opps = <&rpmpd_opp_svs_plus>; - opp-peak-kBps = <5285156>; - }; - - opp-537600000 { - opp-hz = /bits/ 64 <537600000>; - required-opps = <&rpmpd_opp_svs>; - opp-peak-kBps = <3972656>; - }; - - opp-355200000 { - opp-hz = /bits/ 64 <355200000>; - required-opps = <&rpmpd_opp_low_svs>; - opp-peak-kBps = <2136718>; - }; - }; - }; - - gmu_wrapper: gmu@596a000 { - compatible = "qcom,adreno-gmu-wrapper"; - reg = <0x0 0x0596a000 0x0 0x30000>; - reg-names = "gmu"; - power-domains = <&gpucc GPU_CX_GDSC>, - <&gpucc GPU_GX_GDSC>; - power-domain-names = "cx", - "gx"; - }; - - gpucc: clock-controller@5990000 { - compatible = "qcom,shikra-gpucc"; - reg = <0x0 0x05990000 0x0 0x9000>; - clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, - <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - power-domains = <&rpmpd RPMPD_VDDCX>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - adreno_smmu: iommu@59a0000 { - compatible = "qcom,shikra-smmu-500", "qcom,adreno-smmu", - "qcom,smmu-500", "arm,mmu-500"; - reg = <0x0 0x059a0000 0x0 0x10000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - - interrupts = , - , - , - , - , - , - , - , - ; - - clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, - <&gcc GCC_GPU_MEMNOC_GFX_CLK>, - <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, - <&gpucc GPU_CC_AHB_CLK>; - clock-names = "hlos", - "bus", - "iface", - "ahb"; - - power-domains = <&gpucc GPU_CX_GDSC>; - }; - - ethernet0: ethernet@5d00000 { - compatible = "qcom,shikra-ethqos"; - reg = <0x0 0x05d00000 0x0 0x10000>, - <0x0 0x05d16000 0x0 0x100>; - reg-names = "stmmaceth", "rgmii"; - - interrupts = ; - interrupt-names = "macirq"; - - clocks = <&gcc GCC_EMAC0_AXI_CLK>, - <&gcc GCC_EMAC0_AHB_CLK>, - <&gcc GCC_EMAC0_PTP_CLK>, - <&gcc GCC_EMAC0_RGMII_CLK>, - <&gcc GCC_EMAC0_AXI_CLK>, - <&gcc GCC_EMAC0_AXI_SYS_NOC_CLK>, - <&gcc GCC_PCIE_TILE_AXI_SYS_NOC_CLK>; - clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii", - "axi", "axi-noc", "pcie-tile-axi-noc"; - - power-domains = <&gcc GCC_EMAC0_GDSC>; - resets = <&gcc GCC_EMAC0_BCR>; - iommus = <&apps_smmu 0x0380 0x0007>; - - interconnects = <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_EMAC0_CFG QCOM_ICC_TAG_ALWAYS>, - <&system_noc MASTER_EMAC_0 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "cpu-mac", "mac-mem"; - - snps,tso; - snps,pbl = <32>; - rx-fifo-depth = <8192>; - tx-fifo-depth = <8192>; - - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - ethernet1: ethernet@5d20000 { - compatible = "qcom,shikra-ethqos"; - reg = <0x0 0x05d20000 0x0 0x10000>, - <0x0 0x05d36000 0x0 0x100>; - reg-names = "stmmaceth", "rgmii"; - - interrupts = ; - interrupt-names = "macirq"; - - clocks = <&gcc GCC_EMAC1_AXI_CLK>, - <&gcc GCC_EMAC1_AHB_CLK>, - <&gcc GCC_EMAC1_PTP_CLK>, - <&gcc GCC_EMAC1_RGMII_CLK>, - <&gcc GCC_EMAC1_AXI_CLK>, - <&gcc GCC_EMAC1_AXI_SYS_NOC_CLK>, - <&gcc GCC_PCIE_TILE_AXI_SYS_NOC_CLK>; - clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii", - "axi", "axi-noc", "pcie-tile-axi-noc"; - - power-domains = <&gcc GCC_EMAC1_GDSC>; - resets = <&gcc GCC_EMAC1_BCR>; - iommus = <&apps_smmu 0x03a0 0x0007>; - - interconnects = <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>, - <&system_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "cpu-mac", "mac-mem"; - - snps,tso; - snps,pbl = <32>; - rx-fifo-depth = <8192>; - tx-fifo-depth = <8192>; - - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mdss: display-subsystem@5e00000 { - compatible = "qcom,shikra-mdss", "qcom,qcm2290-mdss"; - reg = <0x0 0x05e00000 0x0 0x1000>; - reg-names = "mdss"; - interrupts = ; - interrupt-controller; - #interrupt-cells = <1>; - - clocks = <&gcc GCC_DISP_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>; - clock-names = "iface", - "bus", - "core"; - - resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; - - power-domains = <&dispcc MDSS_GDSC>; - - iommus = <&apps_smmu 0x420 0x2>; - - interconnects = <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG - &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; - interconnect-names = "mdp0-mem", - "cpu-cfg"; - - #address-cells = <2>; - #size-cells = <2>; - ranges; - - status = "disabled"; - - mdp: display-controller@5e01000 { - compatible = "qcom,shikra-dpu", "qcom,qcm2290-dpu"; - reg = <0x0 0x05e01000 0x0 0x8f000>, - <0x0 0x05eb0000 0x0 0x3000>; - reg-names = "mdp", - "vbif"; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - clocks = <&gcc GCC_DISP_HF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", - "iface", - "core", - "lut", - "vsync"; - - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmpd QCM2290_VDDCX>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&mdss_dsi0_in>; - }; - }; - }; - - mdp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmpd_opp_min_svs>; - }; - - opp-192000000 { - opp-hz = /bits/ 64 <192000000>; - required-opps = <&rpmpd_opp_low_svs>; - }; - - opp-256000000 { - opp-hz = /bits/ 64 <256000000>; - required-opps = <&rpmpd_opp_svs>; - }; - - opp-307200000 { - opp-hz = /bits/ 64 <307200000>; - required-opps = <&rpmpd_opp_svs_plus>; - }; - - opp-384000000 { - opp-hz = /bits/ 64 <384000000>; - required-opps = <&rpmpd_opp_nom>; - }; - }; - }; - - mdss_dsi0: dsi@5e94000 { - compatible = "qcom,shikra-dsi-ctrl", - "qcom,qcm2290-dsi-ctrl", - "qcom,mdss-dsi-ctrl"; - reg = <0x0 0x05e94000 0x0 0x400>; - reg-names = "dsi_ctrl"; - - interrupt-parent = <&mdss>; - interrupts = <4>; - - clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, - <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK>, - <&dispcc DISP_CC_MDSS_ESC0_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&gcc GCC_DISP_HF_AXI_CLK>; - clock-names = "byte", - "byte_intf", - "pixel", - "core", - "iface", - "bus"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, - <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, - <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; - - operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd QCM2290_VDDCX>; - phys = <&mdss_dsi0_phy>; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - - dsi_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmpd_opp_min_svs>; - }; - - opp-164000000 { - opp-hz = /bits/ 64 <164000000>; - required-opps = <&rpmpd_opp_low_svs>; - }; - - opp-187500000 { - opp-hz = /bits/ 64 <187500000>; - required-opps = <&rpmpd_opp_svs>; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - mdss_dsi0_in: endpoint { - remote-endpoint = <&dpu_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - mdss_dsi0_out: endpoint { - }; - }; - }; - }; - - mdss_dsi0_phy: phy@5e94400 { - compatible = "qcom,dsi-phy-14nm-2290"; - reg = <0x0 0x05e94400 0x0 0x100>, - <0x0 0x05e94500 0x0 0x300>, - <0x0 0x05e94800 0x0 0x188>; - reg-names = "dsi_phy", - "dsi_phy_lane", - "dsi_pll"; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "iface", - "ref"; - - power-domains = <&rpmpd QCM2290_VDDMX>; - required-opps = <&rpmpd_opp_nom>; - - #clock-cells = <1>; - #phy-cells = <0>; - - status = "disabled"; - }; - }; - - dispcc: clock-controller@5f00000 { - compatible = "qcom,shikra-dispcc", "qcom,qcm2290-dispcc"; - reg = <0x0 0x05f00000 0x0 0x20000>; - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&rpmcc RPM_SMD_XO_A_CLK_SRC>, - <&gcc GCC_DISP_GPLL0_CLK_SRC>, - <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, - <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, - <0>, - <0>, - <&sleep_clk>; - clock-names = "bi_tcxo", - "bi_tcxo_ao", - "gcc_disp_gpll0_clk_src", - "gcc_disp_gpll0_div_clk_src", - "dsi0_phy_pll_out_byteclk", - "dsi0_phy_pll_out_dsiclk", - "dsi1_phy_pll_out_byteclk", - "dsi1_phy_pll_out_dsiclk", - "sleep_clk"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - qaif_cpu: audio@a000000 { - compatible = "qcom,shikra-qaif-cpu"; - reg = <0x0 0x0a000000 0x0 0x20000>; - - interrupts = ; - - clocks = <&gcc GCC_LPASS_CONFIG_CLK>, - <&gcc GCC_LPASS_CORE_AXIM_CLK>, - <&audiocorecc AUDIO_CORE_CC_AUD_DMA_CLK>, - <&audiocorecc AUDIO_CORE_CC_AUD_DMA_MEM_CLK>, - <&audiocorecc AUDIO_CORE_CC_BUS_CLK>, - <&audiocorecc AUDIO_CORE_CC_AIF_IF0_EBIT_CLK>, - <&audiocorecc AUDIO_CORE_CC_AIF_IF0_IBIT_CLK>, - <&audiocorecc AUDIO_CORE_CC_AIF_IF1_EBIT_CLK>, - <&audiocorecc AUDIO_CORE_CC_AIF_IF1_IBIT_CLK>, - <&audiocorecc AUDIO_CORE_CC_AIF_IF2_EBIT_CLK>, - <&audiocorecc AUDIO_CORE_CC_AIF_IF2_IBIT_CLK>, - <&audiocorecc AUDIO_CORE_CC_AIF_IF3_EBIT_CLK>, - <&audiocorecc AUDIO_CORE_CC_AIF_IF3_IBIT_CLK>, - <&audiocorecc AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK>, - <&audiocorecc AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK>; - clock-names = "lpass_config_clk", - "lpass_core_axim_clk", - "aud_dma_clk", - "aud_dma_mem_clk", - "bus_clk", - "aif_if0_ebit_clk", - "aif_if0_ibit_clk", - "aif_if1_ebit_clk", - "aif_if1_ibit_clk", - "aif_if2_ebit_clk", - "aif_if2_ibit_clk", - "aif_if3_ebit_clk", - "aif_if3_ibit_clk", - "ext_mclka_clk", - "ext_mclkb_clk"; - - iommus = <&apps_smmu 0x1c0 0x0>; - - #sound-dai-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - rxmacro: codec@a040000 { - compatible = "qcom,shikra-lpass-rx-macro"; - reg = <0x0 0x0a040000 0x0 0x1000>; - - pinctrl-0 = <&rx_swr_active>; - pinctrl-names = "default"; - - clocks = <&audiocorecc AUDIO_CORE_CC_RX_MCLK_CLK>, - <&audiocorecc AUDIO_CORE_CC_RX_MCLK_2X_CLK>, - <&vamacro>; - clock-names = "mclk", - "npl", - "fsgen"; - - #clock-cells = <0>; - clock-output-names = "mclk"; - #sound-dai-cells = <1>; - status = "disabled"; - }; - - swr0: soundwire@a060000 { - compatible = "qcom,soundwire-v3.1.0"; - reg = <0x0 0x0a060000 0x0 0x10000>; - qcom,swr-master-ee-val = <0>; - - interrupts = ; - - clocks = <&rxmacro>; - clock-names = "iface"; - - label = "RX"; - qcom,din-ports = <0>; - qcom,dout-ports = <5>; - - resets = <&audiocorecc AUDIO_CORE_CSR_RX_SWR_CGCR>; - reset-names = "swr_audio_cgcr"; - - qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; - qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; - qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; - qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; - qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; - qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; - qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; - qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; - qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; - - #sound-dai-cells = <1>; - #address-cells = <2>; - #size-cells = <0>; - status = "disabled"; - }; - - vamacro: codec@a078000 { - compatible = "qcom,shikra-lpass-va-macro"; - reg = <0x0 0x0a078000 0x0 0x2000>; - - pinctrl-0 = <&tx_swr_active>; - pinctrl-names = "default"; - - clocks = <&audiocorecc AUDIO_CORE_CC_TX_MCLK_CLK>, - <&audiocorecc AUDIO_CORE_CC_TX_MCLK_2X_CLK>; - clock-names = "mclk", - "npl"; - - #clock-cells = <0>; - #sound-dai-cells = <1>; - clock-output-names = "fsgen"; - status = "disabled"; - }; - - swr1: soundwire@a080000 { - compatible = "qcom,soundwire-v3.1.0"; - reg = <0x0 0x0a080000 0x0 0x10000>; - qcom,swr-master-ee-val = <0>; - - interrupts = , - ; - interrupt-names = "core", "wakeup"; - - clocks = <&vamacro>; - clock-names = "iface"; - - label = "VA_TX"; - - qcom,din-ports = <4>; - qcom,dout-ports = <0>; - - resets = <&audiocorecc AUDIO_CORE_CSR_TX_SWR_CGCR>; - reset-names = "swr_audio_cgcr"; - - qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; - qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; - qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; - qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; - - #sound-dai-cells = <1>; - #address-cells = <2>; - #size-cells = <0>; - status = "disabled"; - }; - - audiocorecc: clock-controller@a0a0000 { - compatible = "qcom,shikra-cqm-audiocorecc"; - reg = <0x0 0x0a0a0000 0x0 0x10000>, - <0x0 0x0a0b4000 0x0 0x1000>; - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&sleep_clk>, - <0>; - #clock-cells = <1>; - #reset-cells = <1>; - status = "disabled"; - }; - - iris: video-codec@5a00000 { - compatible = "qcom,shikra-iris", "qcom,qcm2290-venus"; - reg = <0x0 0x5a00000 0x0 0x200000>; - interrupts = ; - - power-domains = <&gcc GCC_VENUS_GDSC>, - <&gcc GCC_VCODEC0_GDSC>, - <&rpmpd QCM2290_VDDCX>; - power-domain-names = "venus", - "vcodec0", - "cx"; - operating-points-v2 = <&venus_opp_table>; - - clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, - <&gcc GCC_VIDEO_AHB_CLK>, - <&gcc GCC_VENUS_CTL_AXI_CLK>, - <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>, - <&gcc GCC_VIDEO_VCODEC0_SYS_CLK>, - <&gcc GCC_VCODEC0_AXI_CLK>; - clock-names = "core", - "iface", - "bus", - "throttle", - "vcodec0_core", - "vcodec0_bus"; - - memory-region = <&video_mem>; - interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG - &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, - <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG - &config_noc SLAVE_VENUS_CFG RPM_ACTIVE_TAG>; - interconnect-names = "video-mem", - "cpu-cfg"; - - iommus = <&apps_smmu 0x780 0x0020>; - - venus_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-133333333 { - opp-hz = /bits/ 64 <133333333>; - required-opps = <&rpmpd_opp_low_svs>; - }; - - opp-240000000 { - opp-hz = /bits/ 64 <240000000>; - required-opps = <&rpmpd_opp_svs>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmpd_opp_svs_plus>; - }; - - opp-384000000 { - opp-hz = /bits/ 64 <384000000>; - required-opps = <&rpmpd_opp_nom>; - }; - }; - }; - - sram@c11e000 { - compatible = "qcom,shikra-imem", "mmio-sram"; - reg = <0x0 0x0c11e000 0x0 0x1000>; - ranges = <0x0 0x0 0x0c11e000 0x1000>; - - no-memory-wc; - - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; pil-sram@94c { compatible = "qcom,pil-reloc-info"; @@ -3559,29 +821,6 @@ ; }; - wifi: wifi@c800000 { - compatible = "qcom,wcn3990-wifi"; - reg = <0x0 0x0c800000 0x0 0x800000>; - reg-names = "membase"; - memory-region = <&wlan_mem>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - ; - iommus = <&apps_smmu 0x1a0 0x1>; - qcom,msa-fixed-perm; - - status = "disabled"; - }; - intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; reg = <0x0 0xf200000 0x0 0x10000>, @@ -3682,301 +921,6 @@ status = "disabled"; }; }; - - epss_l3: interconnect@fd90000 { - compatible = "qcom,shikra-epss-l3"; - reg = <0x0 0x0fd90000 0x0 0x1000>; - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - #interconnect-cells = <1>; - }; - - cpufreq_hw: cpufreq@fd91000 { - compatible = "qcom,shikra-epss"; - reg = <0x0 0x0fd91000 0x0 0x1000>, - <0x0 0x0fd92000 0x0 0x1000>; - reg-names = "freq-domain0", - "freq-domain1"; - - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; - clock-names = "xo", "alternate"; - - interrupts = , - ; - interrupt-names = "dcvsh-irq-0", - "dcvsh-irq-1"; - - #freq-domain-cells = <1>; - #clock-cells = <1>; - }; - }; - - thermal_zones: thermal-zones { - aoss0-thermal { - thermal-sensors = <&tsens0 0>; - - trips { - trip-point0 { - temperature = <110000>; - hysteresis = <5000>; - type = "hot"; - }; - - aoss0-critical { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - cpu-0-0-thermal { - thermal-sensors = <&tsens0 1>; - - trips { - trip-point0 { - temperature = <110000>; - hysteresis = <5000>; - type = "hot"; - }; - - cpu00-critical { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - cpu-0-1-thermal { - thermal-sensors = <&tsens0 2>; - - trips { - trip-point0 { - temperature = <110000>; - hysteresis = <5000>; - type = "hot"; - }; - - cpu01-critical { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - cpu-1-0-thermal { - thermal-sensors = <&tsens0 3>; - - trips { - trip-point0 { - temperature = <110000>; - hysteresis = <5000>; - type = "hot"; - }; - - cpu10-critical { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - cpu-1-1-thermal { - thermal-sensors = <&tsens0 4>; - - trips { - trip-point0 { - temperature = <110000>; - hysteresis = <5000>; - type = "hot"; - }; - - cpu11-critical { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - cpuss0-thermal { - thermal-sensors = <&tsens0 5>; - - trips { - trip-point0 { - temperature = <110000>; - hysteresis = <5000>; - type = "hot"; - }; - - cpuss0-critical { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - gpuss-thermal { - polling-delay-passive = <10>; - thermal-sensors = <&tsens0 6>; - - trips { - trip-point0 { - temperature = <110000>; - hysteresis = <5000>; - type = "hot"; - }; - - gpuss_alert0: gpuss-alert0 { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpuss-critical { - temperature = <120000>; - hysteresis = <0>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpuss_alert0>; - cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - nsp-thermal { - thermal-sensors = <&tsens0 7>; - - trips { - trip-point0 { - temperature = <110000>; - hysteresis = <5000>; - type = "hot"; - }; - - nsp-critical { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - mdmss0-thermal { - thermal-sensors = <&tsens0 8>; - - trips { - trip-point0 { - temperature = <110000>; - hysteresis = <5000>; - type = "hot"; - }; - - mdmss0-critical { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - mdmss1-thermal { - thermal-sensors = <&tsens0 9>; - - trips { - trip-point0 { - temperature = <110000>; - hysteresis = <5000>; - type = "hot"; - }; - - mdmss1-critical { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - camera-thermal { - thermal-sensors = <&tsens0 10>; - - trips { - trip-point0 { - temperature = <110000>; - hysteresis = <5000>; - type = "hot"; - }; - - camera-critical { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - video-thermal { - thermal-sensors = <&tsens0 11>; - - trips { - trip-point0 { - temperature = <110000>; - hysteresis = <5000>; - type = "hot"; - }; - - video-critical { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - cpu-0-2-thermal { - thermal-sensors = <&tsens0 12>; - - trips { - trip-point0 { - temperature = <110000>; - hysteresis = <5000>; - type = "hot"; - }; - - cpu02-critical { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; - - cpuss1-thermal { - thermal-sensors = <&tsens0 13>; - - trips { - trip-point0 { - temperature = <110000>; - hysteresis = <5000>; - type = "hot"; - }; - - cpuss1-critical { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; - }; - }; - }; }; timer { diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 0faa3a40ff824..4276d5b966569 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -318,7 +318,7 @@ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_SMP2P>; interrupt-controller; #interrupt-cells = <2>; - #power-domain-cells = <0>; + power-domains = <&cluster_pd>; interrupt-parent = <&intc>; qcom,mpm-pin-count = <96>; qcom,mpm-pin-map = <5 296>, /* Soundwire wake_irq */ @@ -505,7 +505,6 @@ cluster_pd: power-domain-cpu-cluster0 { #power-domain-cells = <0>; - power-domains = <&mpm>; domain-idle-states = <&cluster_sleep_0>; }; }; diff --git a/drivers/irqchip/irq-qcom-mpm.c b/drivers/irqchip/irq-qcom-mpm.c index 181320528a47a..f43c4a1c35f78 100644 --- a/drivers/irqchip/irq-qcom-mpm.c +++ b/drivers/irqchip/irq-qcom-mpm.c @@ -4,6 +4,8 @@ * Copyright (c) 2010-2020, The Linux Foundation. All rights reserved. */ +#include +#include #include #include #include @@ -11,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -18,10 +21,13 @@ #include #include #include +#include #include #include #include +#include + /* * This is the driver for Qualcomm MPM (MSM Power Manager) interrupt controller, * which is commonly found on Qualcomm SoCs built on the RPM architecture. @@ -63,11 +69,23 @@ * */ -#define MPM_REG_ENABLE 0 -#define MPM_REG_FALLING_EDGE 1 -#define MPM_REG_RISING_EDGE 2 -#define MPM_REG_POLARITY 3 -#define MPM_REG_STATUS 4 +#define MPM_TIMER_REGS 2 + +enum qcom_mpm_reg { + MPM_REG_TIMER = 0, + MPM_REG_ENABLE, + MPM_REG_FALLING_EDGE, + MPM_REG_RISING_EDGE, + MPM_REG_POLARITY, + MPM_REG_STATUS, +}; + +#define USECS_TO_CYCLES(time_usecs) xloops_to_cycles((time_usecs) * 0x10C7UL) + +static inline unsigned long xloops_to_cycles(u64 xloops) +{ + return (xloops * loops_per_jiffy * HZ) >> 32; +} /* MPM pin map to GIC hwirq */ struct mpm_gic_map { @@ -76,6 +94,7 @@ struct mpm_gic_map { }; struct qcom_mpm_priv { + struct device *dev; void __iomem *base; raw_spinlock_t lock; struct mbox_client mbox_client; @@ -84,21 +103,41 @@ struct qcom_mpm_priv { unsigned int map_cnt; unsigned int reg_stride; struct irq_domain *domain; - struct generic_pm_domain genpd; + struct notifier_block genpd_nb; + struct notifier_block mpm_pm; + atomic_t cpus_in_pm; }; -static u32 qcom_mpm_read(struct qcom_mpm_priv *priv, unsigned int reg, - unsigned int index) +static unsigned int qcom_mpm_offset(struct qcom_mpm_priv *priv, enum qcom_mpm_reg reg, + unsigned int index) { - unsigned int offset = (reg * priv->reg_stride + index + 2) * 4; + unsigned int reg_offset; + + /* + * Per the vMPM register map, TIMER[0..1] starts at register index 0 and all pin-specific + * registers start after the two TIMER regs. Pin-specific register IDs start at + * MPM_REG_ENABLE, so subtract it to convert to a zero-based pin-register group index. + */ + if (reg == MPM_REG_TIMER) + reg_offset = index; + else + reg_offset = MPM_TIMER_REGS + + (reg - MPM_REG_ENABLE) * priv->reg_stride + index; + + return reg_offset * sizeof(u32); +} + +static u32 qcom_mpm_read(struct qcom_mpm_priv *priv, enum qcom_mpm_reg reg, unsigned int index) +{ + unsigned int offset = qcom_mpm_offset(priv, reg, index); return readl_relaxed(priv->base + offset); } -static void qcom_mpm_write(struct qcom_mpm_priv *priv, unsigned int reg, +static void qcom_mpm_write(struct qcom_mpm_priv *priv, enum qcom_mpm_reg reg, unsigned int index, u32 val) { - unsigned int offset = (reg * priv->reg_stride + index + 2) * 4; + unsigned int offset = qcom_mpm_offset(priv, reg, index); writel_relaxed(val, priv->base + offset); @@ -139,7 +178,7 @@ static void qcom_mpm_unmask(struct irq_data *d) irq_chip_unmask_parent(d); } -static void mpm_set_type(struct qcom_mpm_priv *priv, bool set, unsigned int reg, +static void mpm_set_type(struct qcom_mpm_priv *priv, bool set, enum qcom_mpm_reg reg, unsigned int index, unsigned int shift) { unsigned long flags, val; @@ -292,10 +331,38 @@ static irqreturn_t qcom_mpm_handler(int irq, void *dev_id) return ret; } -static int mpm_pd_power_off(struct generic_pm_domain *genpd) +static void mpm_write_next_wakeup(struct qcom_mpm_priv *priv) +{ + ktime_t now, wakeup = KTIME_MAX; + u64 wakeup_us, wakeup_cycles = ~0; + u32 lo, hi; + + /* Set highest time when system (timekeeping) is suspended */ + if (system_state == SYSTEM_SUSPEND) + goto exit; + + /* Find the relative wakeup in kernel time scale */ + wakeup = dev_pm_genpd_get_next_hrtimer(priv->dev); + + /* Find the relative wakeup in kernel time scale */ + now = ktime_get(); + wakeup = ktime_sub(wakeup, now); + wakeup_us = ktime_to_us(wakeup); + + /* Convert the wakeup to arch timer scale */ + wakeup_cycles = USECS_TO_CYCLES(wakeup_us); + wakeup_cycles += arch_timer_read_counter(); + +exit: + lo = wakeup_cycles; + hi = wakeup_cycles >> 32; + + qcom_mpm_write(priv, MPM_REG_TIMER, 0, lo); + qcom_mpm_write(priv, MPM_REG_TIMER, 1, hi); +} + +static int handle_rpm_notification(struct qcom_mpm_priv *priv) { - struct qcom_mpm_priv *priv = container_of(genpd, struct qcom_mpm_priv, - genpd); int i, ret; for (i = 0; i < priv->reg_stride; i++) @@ -306,11 +373,60 @@ static int mpm_pd_power_off(struct generic_pm_domain *genpd) if (ret < 0) return ret; + mpm_write_next_wakeup(priv); mbox_client_txdone(priv->mbox_chan, 0); - return 0; } +static int mpm_pd_power_cb(struct notifier_block *nb, unsigned long action, void *d) +{ + struct qcom_mpm_priv *priv = container_of(nb, struct qcom_mpm_priv, + genpd_nb); + + switch (action) { + case GENPD_NOTIFY_PRE_OFF: + if (handle_rpm_notification(priv)) + return NOTIFY_BAD; + } + + return NOTIFY_OK; +} + +static int mpm_cpu_pm_callback(struct notifier_block *nfb, unsigned long action, void *v) +{ + struct qcom_mpm_priv *priv = container_of(nfb, struct qcom_mpm_priv, mpm_pm); + int cpus_in_pm; + + switch (action) { + case CPU_PM_ENTER: + cpus_in_pm = atomic_inc_return(&priv->cpus_in_pm); + /* + * NOTE: comments for num_online_cpus() point out that it's + * only a snapshot so we need to be careful. It should be OK + * for us to use, though. It's important for us not to miss + * if we're the last CPU going down so it would only be a + * problem if a CPU went offline right after we did the check + * AND that CPU was not idle AND that CPU was the last non-idle + * CPU. That can't happen. CPUs would have to come out of idle + * before the CPU could go offline. + */ + if (cpus_in_pm < num_online_cpus()) + return NOTIFY_OK; + break; + case CPU_PM_ENTER_FAILED: + case CPU_PM_EXIT: + atomic_dec(&priv->cpus_in_pm); + return NOTIFY_OK; + default: + return NOTIFY_DONE; + } + + if (handle_rpm_notification(priv)) + return NOTIFY_BAD; + + return NOTIFY_OK; +} + static bool gic_hwirq_is_mapped(struct mpm_gic_map *maps, int cnt, u32 hwirq) { int i; @@ -327,7 +443,6 @@ static int qcom_mpm_probe(struct platform_device *pdev, struct device_node *pare struct device_node *np = pdev->dev.of_node; struct device *dev = &pdev->dev; struct irq_domain *parent_domain; - struct generic_pm_domain *genpd; struct device_node *msgram_np; struct qcom_mpm_priv *priv; unsigned int pin_cnt; @@ -339,6 +454,8 @@ static int qcom_mpm_probe(struct platform_device *pdev, struct device_node *pare if (!priv) return -ENOMEM; + priv->dev = &pdev->dev; + ret = of_property_read_u32(np, "qcom,mpm-pin-count", &pin_cnt); if (ret) { dev_err(dev, "failed to read qcom,mpm-pin-count: %d\n", ret); @@ -415,26 +532,6 @@ static int qcom_mpm_probe(struct platform_device *pdev, struct device_node *pare if (irq < 0) return irq; - genpd = &priv->genpd; - genpd->flags = GENPD_FLAG_IRQ_SAFE; - genpd->power_off = mpm_pd_power_off; - - genpd->name = devm_kasprintf(dev, GFP_KERNEL, "%s", dev_name(dev)); - if (!genpd->name) - return -ENOMEM; - - ret = pm_genpd_init(genpd, NULL, false); - if (ret) { - dev_err(dev, "failed to init genpd: %d\n", ret); - return ret; - } - - ret = of_genpd_add_provider_simple(np, genpd); - if (ret) { - dev_err(dev, "failed to add genpd provider: %d\n", ret); - goto remove_genpd; - } - priv->mbox_client.dev = dev; priv->mbox_client.knows_txdone = true; priv->mbox_chan = mbox_request_channel(&priv->mbox_client, 0); @@ -469,14 +566,24 @@ static int qcom_mpm_probe(struct platform_device *pdev, struct device_node *pare goto remove_domain; } + if (of_find_property(np, "power-domains", NULL)) { + devm_pm_runtime_enable(dev); + priv->genpd_nb.notifier_call = mpm_pd_power_cb; + ret = dev_pm_genpd_add_notifier(dev, &priv->genpd_nb); + } else { + priv->mpm_pm.notifier_call = mpm_cpu_pm_callback; + ret = cpu_pm_register_notifier(&priv->mpm_pm); + } + + if (ret) + goto remove_domain; + return 0; remove_domain: irq_domain_remove(priv->domain); free_mbox: mbox_free_channel(priv->mbox_chan); -remove_genpd: - pm_genpd_remove(genpd); return ret; }