(WIP) [Interp] Port axi-stream-s2 BNW bug for interpreter, rewrite using repeat loops

[ngernest]

This PR aims to write the protocols for the axi-stream-s2 BNW bug (#158) to use repeat loops in order to express backpressure.

Edit: I merged #194 & #197 into this branch so that I could work on it, please review/merge those branches before looking at this PR

TODOs:

• See if we can use the exact same .prot files for the monitor + interpreter (i.e. update the monitor version to refer to the pins in the internal Verilog file instead of the external wrapper module)
• See [Monitor] Create CLI flag to ignore #[idle] pragma (always print idle() transactions) #189
• Create alternate version of s2_buggy.prot / s2_fixed.prot that uses repeat loops

[ngernest]

Edit: the waveforms produced by the BNW test-benches terminate immediately after the bug occurs, so the buggy waveform can't be realized by a monitor failure (since no successful data transfer happens when data = 7, which is ideally what we want in the fixed waveform). We discussed today (3/6) how one approach would be to modify the TB so that we get a longer waveform, although we should work on the other BNW bugs for now.