ppcexec: Respect CPU-specific POW behavior#188
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Followup to dingusdev#186 - select `MSR[POW]` handling mode once during CPU initialization instead of treating every processor as `HID0`-gated. We match documented (and QEMU) behavior: - 603/7xx CPUs require `HID0` doze, nap, or sleep bits before we enter the emulator sleep loop - 604-family CPUs use just for `POW` directly - 601 does not support `POW` at all
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Followup to #186 - select
MSR[POW]handling mode once during CPU initialization instead of treating every processor asHID0-gated.We match documented (and QEMU) behavior:
HID0doze, nap, or sleep bits before we enter the emulator sleep loopPOWdirectlyPOWat all