Test CI/CD checks#1479
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Add device tree bindings for the camera clock controller on Qualcomm Glymur SoC. Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260402-glymur_camcc-v1-1-e8da05a21da7@oss.qualcomm.com
Add support for the camera clock controller for camera clients to be able to request for camcc clocks on Glymur platform. Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260402-glymur_camcc-v1-2-e8da05a21da7@oss.qualcomm.com
The GX GDSC is a special power domain that should only be disabled by OS during GMU recovery. In all other scenarios, the GMU firmware is responsible for handling its disable sequence, and OS must not interfere. During the resume_noirq() phase of system resume, the GenPD framework enables all power domains and later disables them in the complete() phase if there are no active votes from OS. This behavior can incorrectly disable the GX GDSC while the GMU firmware is still using it. To prevent this, implement a custom disable callback for GX GDSC that relies on GenPD’s synced_poweroff flag. The GMU driver sets this flag only during recovery, allowing OS to explicitly disable GX GDSC in hardware in that case. In all other situations, the disable callback will avoid touching GX GDSC hardware. Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260427-gfx-clk-fixes-v2-1-797e54b3d464@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
The GX GDSC represents a special GPU power domain that must not be disabled during normal runtime PM flows. As per the GMU architecture, GX GDSC should only be force-disabled during GMU/GPU recovery, where the OS explicitly resets the GX power domain. However, when managed by the generic GDSC runtime PM path, GX GDSC may be disabled during GMU runtime suspend, resulting in warnings such as: gx_clkctl_gx_gdsc status stuck at 'on' and failures in gdsc_toggle_logic() during rpm suspend. Use the newly added custom disable callback for gx_gdsc to ensure the GDSC is toggled only in recovery scenarios, while preventing unintended disable attempts during normal GMU runtime PM operations. Reported-by: Pengyu Luo <mitltlatltl@gmail.com> Closes: https://lore.kernel.org/all/CAH2e8h4Vp9fJYAUUbOmoHSKB25wakPBvmpwa62BTRqgRQbMWuw@mail.gmail.com/ Reported-by: Alexander Koskovich <akoskovich@pm.me> Closes: https://lore.kernel.org/all/gwVAH2mJerU4dBInw8pKmOs5aQK55Q7W6q_UQAlLFCsEgX6eyvSgXAWbNNMqAX4WmPlYCKUSMhfkr5Jry4Ps5EqnxYZqEEDd3Whwv7ZXGlc=@pm.me/ Fixes: 5af11ac ("clk: qcom: Add a driver for SM8750 GPU clocks") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260427-gfx-clk-fixes-v2-2-797e54b3d464@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…robe When the clock controller is probed with 'use_rpm' enabled, the runtime PM reference is currently released using pm_runtime_put(), which may return before the runtime suspend has completed. When the clock controller device is registered through this function, calling pm_runtime_disable() immediately after pm_runtime_put() prevents the runtime suspend from completing, leaving the clock controller active and the HW rails in the ON state. Use pm_runtime_put_sync() instead to ensure the runtime PM “putV completes synchronously during probe. This does not have any functional impact, but it guarantees that the device is fully runtime-suspended before returning. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260427-gfx-clk-fixes-v2-3-797e54b3d464@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…h IFPC The GX GDSC control is handled through a dedicated clock controller, and the enable/disable sequencing depends on correct rail voting. The driver votes for the GX/GMxC rails and CX GDSC before toggling the GX GDSC. Currently, during GMU runtime PM resume, rails remain enabled due to upstream votes propagated via RPM-enabled devlinks and explicit pm_runtime votes on GX GDSC. This is not an expected behaviour of IFPC(Inter Frame Power Collapse) requirements of GPU as GMU firmware is expected to control these rails, except during the GPU/GMU recovery via the OS and that is where the GX GDSC should be voting for the rails (GX/GMxC and CX GDSC) before toggling the GX GDSC. Thus, disable runtime PM after successfully registering the clock controller. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260427-gfx-clk-fixes-v2-4-797e54b3d464@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
The gcc_eva_ahb_clk and gcc_eva_xo_clk branch clocks should not be registered as standalone GCC branch clocks. Drop these clocks from the GCC clock list and instead add their CBCR registers to the GCC critical clocks list to ensure they remain enabled during early boot. Fixes: efe5043 ("clk: qcom: gcc: Add support for Global Clock Controller") Link: https://lore.kernel.org/lkml/20260526-evacc_glymur-v1-1-b61c7755c403@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…r for Glymur SoC Add the device tree bindings for the enhanced video analytics(EVA) clock controller which is required on Qualcomm Glymur SoC. The controller provides clocks, resets and power domains for the EVA subsystem. Link: https://lore.kernel.org/lkml/20260526-evacc_glymur-v1-2-b61c7755c403@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Add the Enhanced Video Analytics (EVA) clock controller driver for the Glymur SoC. The EVACC manages the PLL, RCGs, branch clocks, GDSCs and resets for the EVA subsystem which handles vision processing workloads. Link: https://lore.kernel.org/lkml/20260526-evacc_glymur-v1-3-b61c7755c403@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…divider Add device tree bindings for the Qualcomm Peripheral Web's PDM GP_MN clock divider. The hardware generates a fractional output frequency from a fixed input clock (typically TCXO4) using the relation Fout = Fin * (M / N), with duty cycle controlled by a separate D register. The clock output is routed over a gpio controlled pin. Link: https://lore.kernel.org/r/20260602-pdm_clk_gp_mnd_v1-v1-1-1522662b6c53@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
The PDM (Pulse Density Modulation) hardware block on Qualcomm SoCs contains a GP_MN clock divider that produces a fractional output frequency from a fixed input clock (typically TCXO4): Fout = Fin * (M / N) The hardware encodes the period in the NDIV register as the 1's complement of (N - M), and controls the duty cycle via a separate DUTY register that counts the number of low-phase native clock cycles over the period N. Add a standalone platform driver for this block that uses rational_best_approximation() to find the closest M/N pair within the 9-bit M and 13-bit N hardware limits, programs the MDIV, NDIV, and DUTY registers via regmap, and implements the full clk_ops surface including determine_rate, set_rate, recalc_rate, get_duty_cycle, and set_duty_cycle. The PDM AHB bus clock is gated around every register access. Link: https://lore.kernel.org/r/20260602-pdm_clk_gp_mnd_v1-v1-2-1522662b6c53@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Qualcomm TSCSS is a time synchronization subsystem composed of two main blocks: the Time Stamp Counter (TSC) and the Event Timestamp Unit (ETU). The TSC block is a timestamp generator that maintains a running counter used for system timekeeping. The ETU block captures timestamps for external events using one of the available timestamp sources. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Add support for the Qualcomm TSCSS hardware, that is a time synchronization subsystem composed of two main blocks: the Time Stamp Counter (TSC) and the Event Timestamp Unit (ETU). Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
…eroff flag is set USB, PCIE GDSCs require the GDSC to left ON in USB host mode and PCIE non-D3 cold usecases even during system suspend. To handle this use the GenPD's synced_poweroff flag which can be set by USB/PCIE drivers if they require the GDSC to be disabled before suspend. If the GDSC is required to be left ON, the USB/PCIE drivers can avoid setting this flag before suspend. Add support for custom gdsc disable callback that disables GDSC based on GenPD's synced_poweroff flag. Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Signed-off-by: Krishna Kurapati <kriskura@qti.qualcomm.com>
…GDSC's Use gdsc_synced_poweroff_disable callback for USB GDSC's on qcs615 platforms so these GDSC's get disabled only when consumer drivers explicitly invoke dev_pm_genpd_synced_poweroff() API before suspend. Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Signed-off-by: Krishna Kurapati <kriskura@qti.qualcomm.com>
…mode bus suspend On targets pre-sm8750, when DUT enters bus suspend in host mode, there is a xHCI crash seen on resume. During bus susend use case if the device is wakeup capable, the GDSC needs to be kept ON to retain memory and avoid SMMU faults. Set synced_poweroff flag to false to ensure GDSC is turned OFF during cable disconnect or non-bus suspend host mode scenario. Signed-off-by: Krishna Kurapati <kriskura@qti.qualcomm.com>
…lcomm Eliza SoC Eliza Video clock controller is on CX and MX rails similar to Milos. Add compatible string for Eliza video clock controller to the existing Milos videocc binding and add the dt-bindings header for Eliza. The video clock controller exposes power domains, so '#power-domain-cells' must be present in the device node. Add it to the required properties list to enforce this in binding validation. There is no ABI breakage and no impact to the existing devices, since the nodes using this binding already specify the '#power-domain-cells' property for videocc. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260609-b4-eliza_mm_cc_v6-v6-1-17df09e5940c@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…roller Add bindings documentation for the Eliza Graphics Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260609-b4-eliza_mm_cc_v6-v6-2-17df09e5940c@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Eliza camera clock controller is on CX and MX rails similar to Milos. Add compatible string for Eliza camera and camera BIST clock controller to the existing Milos camcc binding and add the dt-bindings header for Eliza. The camera clock controller provides power domains, so 'power-domain-cells' must be present in the device tree node. Add this to required properties to enforce it in the binding schema. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260609-b4-eliza_mm_cc_v6-v6-3-17df09e5940c@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…liza Add support for the video clock controller for video clients to be able to request for videocc clocks on Eliza platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260609-b4-eliza_mm_cc_v6-v6-4-17df09e5940c@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Add Graphics Clock Controller (GPUCC) support for Eliza platform. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260609-b4-eliza_mm_cc_v6-v6-5-17df09e5940c@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…or Eliza Add support for the Camera Clock Controller (CAMCC) on the Eliza platform. The CAMCC block on Eliza includes both the primary camera clock controller and the Camera BIST clock controller, which provides the functional MCLK required for camera operations. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260609-b4-eliza_mm_cc_v6-v6-6-17df09e5940c@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
🔨 Build Failure Analysis — PR #1479PR: #1479
VerdictThis PR does not introduce any build errors. The build failure occurred during the automerge/integration phase where multiple topic branches are merged together. The PR file 📎 Detailed analysis: Full report |
🔨 Build Failure Analysis — PR #1479PR: #1479
VerdictNo compilation errors occurred. The build failed during the automerge phase due to 108 merge conflicts across multiple files. The PR changes to 📎 Detailed analysis: Full report |
PR #1479 — validate-patchPR: #1479
Final Summary
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PR #1479 — checker-log-analyzerPR: #1479
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Use the correct alpha_pll_config member name test_ctl_hi_val for GPLL8, GPLL10, and GPLL11. The existing test_ctl_hi1_val assignment is incorrect and prevents the TEST_CTL_HI register value from being configured as intended. Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
🔨 Build Failure Analysis — PR #1479PR: #1479
VerdictNo compilation errors exist. The build failed during the automerge phase with 100+ merge conflicts in files completely unrelated to this PR. The PR changes to 📎 Detailed analysis: Full report |
🔨 Build Failure Analysis — PR #1479PR: #1479
VerdictThis is NOT a compilation failure. The build failed during the automerge stage due to merge conflicts between topic branches. The PR modifies only 📎 Detailed analysis: Full report |
PR #1479 — validate-patchPR: #1479
Final Summary
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PR #1479 — checker-log-analyzerPR: #1479
Detailed report: Full report
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This change is to test the CI/CD.