Prepare qcom-next based on tag 'Linux 7.2-rc3' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git#830
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Purwa's GPU does not support SID 1, which is typically used for LPAC-related traffic. Remove SID 1 from the GPU node's iommus property to accurately describe the hardware. This fixes the splat below, seen with some versions of Gunyah hypervisor: Internal error: synchronous external abort: 0000000096000010 [#1] SMP CPU: 0 UID: 0 PID: 80 Comm: kworker/u33:2 Tainted: G M Tainted: [M]=MACHINE_CHECK Hardware name: Qualcomm Technologies, Inc. Purwa IoT EVK (DT) Workqueue: events_unbound deferred_probe_work_func pstate: 21400005 (nzCv daif +PAN -UAO -TCO +DIT -SSBS BTYPE=--) pc : arm_smmu_write_s2cr+0x9c/0xbc lr : arm_smmu_master_install_s2crs+0x78/0xa4 sp : ffff80008039b570 x29: ffff80008039b570 x28: 0000000000000000 x27: ffffaddd62f1ab78 x26: ffff00080a4ff280 x25: 0000000000000018 x24: ffff00080b896480 x23: ffff00080ba9b7a0 x22: ffff00080bb05160 x21: 0000000000000000 x20: 0000000000000000 x19: 0000000000000001 x18: 00000000ffffffff x17: 0000000000000000 x16: 0000000000000000 x15: ffff80008039b1d0 x14: ffff80010039b37d x13: 00746c7561662d74 x12: 0000000000000000 x11: ffff00080b7fbd98 x10: ffffffffffffffc0 x9 : ffffffffffffffff x8 : 0000000000000228 x7 : 0000000000000e87 x6 : 0000000000000000 x5 : 0000000000000000 x4 : ffff00080a4ff280 x3 : 0000000000000000 x2 : ffff800082a40c04 x1 : 0000000000000000 x0 : ffff800082a40000 Call trace: arm_smmu_write_s2cr+0x9c/0xbc (P) arm_smmu_master_install_s2crs+0x78/0xa4 arm_smmu_attach_dev+0xb0/0x1d8 __iommu_device_set_domain+0x84/0x11c __iommu_group_set_domain_internal+0x60/0x120 __iommu_attach_group+0x88/0x9c iommu_attach_device+0x6c/0xa0 msm_iommu_new.part.0+0x84/0xe4 [msm] msm_iommu_gpu_new+0x3c/0x104 [msm] adreno_iommu_create_vm+0x24/0xc8 [msm] a6xx_create_vm+0x48/0x78 [msm] msm_gpu_init+0x2d8/0x508 [msm] adreno_gpu_init+0x208/0x324 [msm] a6xx_gpu_init+0x604/0x8cc [msm] adreno_bind+0xb4/0x124 [msm] component_bind_all+0x114/0x23c msm_drm_init+0x1b0/0x1ec [msm] msm_drm_bind+0x30/0x3c [msm] try_to_bring_up_aggregate_device+0x164/0x1d0 __component_add+0xa4/0x16c component_add+0x14/0x20 msm_dp_display_probe_tail+0x4c/0xac [msm] msm_dp_auxbus_done_probe+0x14/0x20 [msm] dp_aux_ep_probe+0x4c/0xf4 [drm_dp_aux_bus] really_probe+0xbc/0x29c __driver_probe_device+0x78/0x12c driver_probe_device+0x3c/0x15c __device_attach_driver+0xb8/0x134 bus_for_each_drv+0x88/0xe8 __device_attach+0xa0/0x190 device_initial_probe+0x50/0x54 bus_probe_device+0x38/0xa4 deferred_probe_work_func+0x88/0xc0 process_one_work+0x148/0x28c worker_thread+0x2cc/0x3d4 kthread+0x12c/0x204 ret_from_fork+0x10/0x20 ---[ end trace 0000000000000000 ]--- Fixes: 1aa0b4e ("arm64: dts: qcom: x1p42100: Add GPU support") Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260410-purwa-gpu-dt-fix-v1-1-4637892156cf@oss.qualcomm.com
Add node for the X1P42100 camera subsystem. Link: https://lore.kernel.org/all/20260410-purwa_camss-v1-3-eedcf6d9d8ee@oss.qualcomm.com/ Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
enable camss node for purwa iot evk board camss tpg support. Link: https://lore.kernel.org/all/20260410-purwa_camss-v1-4-eedcf6d9d8ee@oss.qualcomm.com/ Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
Add embedded controller node for Hamoa/Purwa CRDs which adds fan control, temperature sensors, access to EC internal state changes and suspend entry/exit notifications to the EC. Link: https://lore.kernel.org/lkml/20260427-add-driver-for-ec-v8-4-702f74e495f7@oss.qualcomm.com/ Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Co-developed-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com> Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
Add embedded controller node for Hamoa IOT EVK boards which adds fan control, temperature sensors, access to EC internal state changes and suspend entry/exit notifications to the EC. Link: https://lore.kernel.org/lkml/20260427-add-driver-for-ec-v8-5-702f74e495f7@oss.qualcomm.com/ Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com> Tested-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com> Co-developed-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com> Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
… points The Iris block on X1P differs from SM8550/X1E in its clock configuration and requires a dedicated OPP table. The node inherited from the X1E cannot be reused directly, and the fallback compatible "qcom,sm8550-iris" cannot be applied. Override the inherited clocks, clock-names, and operating points, and replaces them with the X1P42100-specific definitions. A new OPP table is provided to support the correct performance levels on this platform. Link: https://lore.kernel.org/linux-arm-msm/20260429-enable_iris_on_purwa-v5-4-438fa96da248@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
Enable video nodes on the purwa-iot-som board. Link: https://lore.kernel.org/linux-arm-msm/20260429-enable_iris_on_purwa-v5-5-438fa96da248@oss.qualcomm.com/ Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Signed-off-by: Wangao Wang <wangao.wang@oss.qualcomm.com>
Switch the iris video codec node in hamoa from the legacy 'iommus' property to 'iommu-map', using IRIS_NON_PIXEL_VCODEC and IRIS_PIXEL function IDs to identify the non-pixel and pixel context bank SMMU stream mappings respectively. Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Signed-off-by: Gourav Kumar <gouravk@qti.qualcomm.com>
On Qualcomm Hamoa SoCs, the memlat governor and the mechanism to control the LLCC and DDR/DDR_QOS is hosted on the CPU Control Processor (CPUCP). Add the vendor protocol node to the existing SCMI transport to enable QCOM SCMI Generic Extension protocol on Hamoa SoCs. Link: https://lore.kernel.org/lkml/20260507062237.78051-9-sibi.sankar@oss.qualcomm.com/ Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Purwa IOT boards support a different thermal junction temperature specification compared to the base Purwa platform due to package level differences. Update the passive trip thresholds to 105°C to align with the higher temperature specification. Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260416-purwa_high_tj-v1-1-b538f98d42da@oss.qualcomm.com
Add video firmware node to enable video kvm on the hamoa. Signed-off-by: Renjiang Han <renjiang@qti.qualcomm.com>
…devices Add label properties to TPDM and CTI nodes in the hamoa device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Link: https://lore.kernel.org/linux-arm-msm/20260414-add-label-to-coresight-device-v2-7-5017d07358f2@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Unlike the CPU, the CDSP does not throttle its speed automatically when it reaches high temperatures in hamoa. Set up CDSP cooling for both instances by throttling the cdsp, when it reaches 95°C. Link: https://lore.kernel.org/linux-devicetree/20260609-qmi-tmd-v3-8-291a2ff4c634@oss.qualcomm.com/ Signed-off-by: Dipa Ramesh Mantre <dipa.mantre@oss.qualcomm.com> Signed-off-by: Xin Liu <xin.liu@oss.qualcomm.com>
…rwa IOT EVK Document the qcom,purwa-iot-evk-ec compatible for the embedded controller found on Purwa IOT EVK boards. Like the CRD, the Purwa IOT EVK carries an on-board embedded controller, provided by ITE and running on a separate MCU, which handles fan control, temperature sensors and EC state-change/suspend notifications. The existing Hamoa IOT EVK documents the same EC via qcom,hamoa-iot-evk-ec. Like the other reference designs, it uses qcom,hamoa-crd-ec as its fallback compatible. Link: https://lore.kernel.org/all/20260703-ec_support_for_purwa_evk-v2-1-c59aac5c6aac@oss.qualcomm.com/ Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
Add embedded controller node for Purwa IOT EVK boards which adds fan control, temperature sensors, access to EC internal state changes and suspend entry/exit notifications to the EC. Link: https://lore.kernel.org/all/20260703-ec_support_for_purwa_evk-v2-2-c59aac5c6aac@oss.qualcomm.com/ Tested-by: Yushan Li <yushan.li@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
Add deepest idle state as GPIO IRQs can work as wakeup capable interrupts in deepest idle state. Update entry/exit-latency-us to follow DSDT for cluster_cl5 idle state. Link: https://lore.kernel.org/r/20260707-hamoa_pdc_v3-v4-7-dfd1f4a3ae89@oss.qualcomm.com Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
X1P42100 (Purwa) shares the X1E80100 (Hamoa) PDC device, but the hardware register bug addressed in commit e9a48ea ("irqchip/qcom-pdc: Workaround hardware register bug on X1E80100") is already fixed in X1P42100 silicon. X1E80100 compatible forces the software workaround. Use the X1P42100 specific compatible string for the PDC node to remove the workaround. Fixes: f08edb5 ("arm64: dts: qcom: Add X1P42100 SoC and CRD") Link: https://lore.kernel.org/r/20260616-purwa-pdc-v2-2-8dda7ef25ce5@oss.qualcomm.com Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
Reference the reserved memory region for audio PD dynamic loading and remote heap requirements. Add the required VMID list for memory ownership transfers. Link: https://lore.kernel.org/all/20260629-hamoa-remoteheap-v1-1-aa868b7a6e65@oss.qualcomm.com/ Signed-off-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com> Signed-off-by: Jianping Li <jianping.li@oss.qualcomm.com>
…APSS debug block" This reverts commit 6c255c6. The driver patch series has been dropped so remove the dt patch as well. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
…APSS debug block" This reverts commit cb96f06. The driver patch has been dropped so remove the dt patch as well. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
…or APSS debug block" This reverts commit 2d7437f. The driver patch has been dropped so remove the dt patch as well. Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Document the platforms that fallback to using the qcom,sa8775p-ctcu compatible for probing. Link: https://lore.kernel.org/all/20260204-enable-ctcu-and-etr-v3-1-0bb95c590ae1@oss.qualcomm.com/ Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
…PHY on Glymur The PCIe PHYs on Glymur require a reference voltage provided by REFGEN, which in turn is powered by two LDOs. Since there is no devicetree node for REFGEN, add the vdda-refgen0p9 and vdda-refgen1p2 supplies for each PCIe PHY node. Link: https://lore.kernel.org/all/20260623-phy_refgen-v2-0-4d15983bf91d@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
The TCSR clkref_en clocks gate the QREF block which provides reference clocks to the PCIe PHYs. Wire up the LDO supplies required by the QREF and refgen blocks on the CRD board. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Mahua has a different QREF topology from Glymur. Override the TCSR compatible to qcom,mahua-tcsr in mahua.dtsi, and wire up the required LDO supplies on the CRD board. Unlike the other PCIe controllers, PCIe5 PHY on Mahua gets its refclk from the CXO0 pad directly and requires no QREF clkref_en voting. Hence, point its ref clock at RPMH_CXO_CLK. Link: https://lore.kernel.org/all/20260702-tcsr_qref_0702-v7-0-776f2811b7af@oss.qualcomm.com/ Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…R for glymur-qcb Wire up the required LDO supplies on the QCB board. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
…R for mahua-qcb Wire up the required LDO supplies on the QCB board. Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
This patch introduces the creation of AEST platform devices, where each device represents a logical "error node device" grouping one or more AEST nodes from the ACPI table. Instead of relying on the optional 'error_node_device' field in the AEST table[1], this commit uses the interrupt number as the sole identifier for the parent device. This design simplifies the driver logic by providing a single, consistent mechanism for grouping nodes. The 'error_node_device' field can be unspecified, but an AEST node is always physically associated with a parent component. The interrupt number serves as a reliable proxy for this association. This approach is based on the safe assumption that distinct hardware components (e.g., SMMU, CMN, GIC) are assigned unique error interrupts and do not share them. [1]: https://developer.arm.com/documentation/den0085/latest Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-2-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
Parse register information from the AEST table in the probe function, create corresponding structures, and mappings AEST record. Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-3-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
Support for various AEST group formats allows for flexible configuration of AEST node address space sizes and maximum record counts per group. Signed-off-by: Ruidong Tian <tianruidong@linux.alibaba.com> Link: https://patch.msgid.link/20260122094656.73399-4-tianruidong@linux.alibaba.com Signed-off-by: Umang Chheda <umang.chheda@oss.qualcomm.com>
# Conflicts: # drivers/remoteproc/qcom_q6v5_pas.c
# Conflicts: # Makefile
# Conflicts: # arch/arm64/boot/dts/qcom/monaco.dtsi
# Conflicts: # Makefile
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile # arch/arm64/boot/dts/qcom/talos.dtsi
# Conflicts: # arch/arm64/boot/dts/qcom/qcs8300-ride.dts # drivers/bluetooth/hci_qca.c # drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
# Conflicts: # drivers/dma/qcom/bam_dma.c # drivers/gpu/drm/bridge/lontium-lt9611c.c # drivers/misc/fastrpc.c # sound/soc/qcom/qdsp6/q6prm.h
# Conflicts: # Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
Test Matrix
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Name SHA Commits
tech/bsp/clk d7c3ea1 29
tech/bsp/devfreq 5a26797 7
tech/bsp/soc-infra ff6ff7b 22
tech/bsp/pinctrl 79149ef 1
tech/bsp/remoteproc cbd11fb 10
tech/bus/peripherals fedd8c6 6
tech/bus/pci/all ebd808f 4
tech/bus/pci/phy 1f1f4b6 7
tech/bus/usb/dwc 9dd47ad 3
tech/bus/usb/phy c3aa7d5 35
tech/debug/hwtracing d9accac 22
tech/pmic/misc 6fb618c 8
tech/mem/iommu 44df12a 8
tech/mm/audio/all 88b8f29 8
tech/mm/camss c394dfb 32
tech/mm/drm 1d1d827 64
tech/mm/fastrpc e014e35 11
tech/mm/video 590953d 36
tech/mm/gpu 0b8d9f4 7
tech/net/ath 638841e 16
tech/pm/power bb88701 13
tech/pm/thermal d36b3ee 7
tech/security/crypto c36112e 14
tech/security/ice beabac0 9
tech/storage/all d86d915 4
tech/all/dt/qcs6490 db0d97d 20
tech/all/dt/qcs9100 166356c 88
tech/all/dt/qcs8300 4099510 22
tech/all/dt/qcs615 9a58c35 9
tech/all/dt/agatti c828f10 1
tech/all/dt/hamoa fa16fdb 36
tech/all/dt/glymur aba48bf 39
tech/all/dt/kaanapali c637991 19
tech/all/dt/pakala 960924d 13
tech/all/config 2f8abb9 69
tech/overlay/dt 6a1064f 77
tech/all/workaround 2a67b15 26
tech/mproc/all 104969c 2
tech/noup/debug/all cbdd4bb 26
tech/hwe/unoq a2d85fe 4
early/hwe/shikra/drivers 46a583d 161
early/hwe/shikra/dt e6da759 122