Register MPM under CPU cluster power domain#832
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PR #832 — validate-patchPR: #832
Final Summary
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PR #832 — checker-log-analyzerPR: #832
Detailed report: Full report
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…ins property Remove #power-domain-cells property and add power-domains property for MPM device. Link: https://lore.kernel.org/lkml/20260713-b4-shikra_lpm_addition-v1-1-3d858df2cbbf@oss.qualcomm.com Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
…domain
MPM irqchip needs to notify RPM (Resource Power Manager) processor to read
the latest wake up capable interrupts when the CPU cluster is entering the
deepest idle state. This is done by sending IPC interrupt to RPM and is
implemented as .power_off() callback by registering MPM as parent power
domain to CPU cluster.
Such implementation introduces a hard probe dependency between MPM irqchip
and CPU cluster power domains. That is MPM irqchip needs to finish probe
before PSCI power domains are probed. MPM irqchip can be build as module
and can get later inserted where as PSCI power domains is not a module.
For in-built driver cases too PSCI domain gets probed first and later MPM
irqchip leading to failure of CPUidle states.
Detailed flow of the non-working scenario:
psci-cpuidle-domain.c probe
--> dt_idle_pd_init_topology()
--> of_genpd_add_subdomain()
--> genpd_get_from_provider()
--> fails to find parent MPM genPD provider
--> returns -EPROBE_DEFER.
irq-qcom-mpm.c probe
--> of_genpd_add_provider_simple()
--> genpd_add_provider()
--> MPM added as a genPD provider.
Now when psci_cpuidle_probe() is called to probe the CPU idle states, it
tries to map the states to the mentioned power-domains.
But since power domains probe has been deferred, psci_cpuidle_probe() too
will return -EPROBE_DEFER.
commit af5376a ("cpuidle: psci: Transition to the faux device
interface") transitioned cpuidle-psci to a faux device interface.
faux_device_create() calls faux_device_create_with_groups(), which ignores
the probe return value, and destroys the device if dev->driver is not set.
This will lead to psci_cpuidle_probe() not being called again, resulting in
all idle-state devices failing to init in SoCs setting MPM as a parent
power domain to CPU cluster.
cpuidle-psci.c init
--> faux_device_create()
...
--> psci_cpuidle_probe()
--> psci_idle_init_cpu()
...
--> psci_dt_cpu_init_topology()
...
-> dev_pm_domain_attach_by_name()
--> __genpd_dev_pm_attach()
--> genpd_get_from_provider()
--> fails to find CPU genPD provider
--> returns -EPROBE_DEFER
--> return value ignored and device
destroyed
Move the RPM notification handling to the GENPD_NOTIFY_PRE_OFF callback and
register MPM under the CPU cluster power domain. Use runtime PM to report
the default RPM_SUSPENDED state to genPD so that the CPU cluster power
domain can enter low power mode.
If MPM has not registered with CPU cluster power domain, utilize the CPU PM
notifications to manage RPM communication when the last CPU goes to power
collapse.
Fixes: a6199bb ("irqchip: Add Qualcomm MPM controller driver")
Link: https://lore.kernel.org/lkml/20260713-b4-shikra_lpm_addition-v1-2-3d858df2cbbf@oss.qualcomm.com
Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
…and pin regs The vMPM layout starts with two timer registers followed by pin register banks (ENABLE/FALLING/RISING/POLARITY/STATUS), each with reg_stride number of entries. Use qcom_mpm_offset() as the common addressing helper for both timer and pin register accesses based on that layout. vMPM has MPM_REG_* values represented as contiguous register IDs, hence replace the macros with enum qcom_mpm_reg and modify the accessor helpers accordingly. Link: https://lore.kernel.org/lkml/20260713-b4-shikra_lpm_addition-v1-3-3d858df2cbbf@oss.qualcomm.com Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
… goes to LPM The next wakeup timer value needs to be set in MPM timer as the arch timer interrupt can not wakeup the SoC if after the deepest CPUidle states the SoC also enters deepest low power state. To wakeup the SoC in such scenarios the earliest wakeup time is set in MPM timer and the Resource Power Manager (RPM processor) takes care of setting the timer in HW. Add MPM timer programming when CPU cluster enters power collapse. Link: https://lore.kernel.org/lkml/20260713-b4-shikra_lpm_addition-v1-4-3d858df2cbbf@oss.qualcomm.com Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
…uster domain Do not mark MPM device as power domain since it leads to idle-states init failure because of probe dependencies. Instead make it as part of CPU cluster power domain to allow RPM notification when CPU cluster goes to power collapse. Link: https://lore.kernel.org/lkml/20260713-b4-shikra_lpm_addition-v1-5-3d858df2cbbf@oss.qualcomm.com Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
Do not mark MPM device as power domain since it leads to idle-states init failure because of probe dependencies. CPU cluster power domain node is kept disabled and hence CPU cluster will never power collapse. Do not register MPM under it in this case. Link: https://lore.kernel.org/lkml/20260713-b4-shikra_lpm_addition-v1-6-3d858df2cbbf@oss.qualcomm.com Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
Add idle states for the CPUs as well as the whole cluster. This enables deeper-than-WFI cpuidle. Add MPM under cluster_pd power domain. Link: https://lore.kernel.org/lkml/20260713-b4-shikra_lpm_addition-v1-7-3d858df2cbbf@oss.qualcomm.com Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
PR #832 — validate-patchPR: #832
Final Summary
|
PR #832 — checker-log-analyzerPR: #832
Detailed report: Full report
|
2 participants
MPM irqchip needs to notify RPM (Resource Power Manager) processor to read
the latest wake up capable interrupts when the CPU cluster is entering the
deepest idle state. This is done by sending IPC interrupt to RPM and is
implemented as .power_off() callback by registering MPM as parent power
domain to CPU cluster.
Such implementation introduces a hard probe dependency between MPM irqchip
and CPU cluster power domains.
Move the RPM notification handling to the GENPD_NOTIFY_PRE_OFF callback and
register MPM under the CPU cluster power domain.
If MPM has not registered with CPU cluster power domain, utilize the CPU PM
notifications to manage RPM communication when the last CPU goes to power
collapse.
Program wakeup timer when CPU cluster goes to LPM.
Add CPU and CPU cluster LPM states for Shikra
Signed-off-by: Sneh Mankad sneh.mankad@oss.qualcomm.com