The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code

Chisel RISC-V Vector 1.0 Implementation

Unit tests generator for RVV 1.0

Read chapters directly from this repo - do not use GitHub Pages link.

x86-64, ARM, and RVV intrinsics viewer

Tenstorrent Blackhole P100/P150 card RISC-V Linux demo 🐧

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)

A translator from ARM NEON intrinsics to RISCV-V Extension implementation

Implements kernels with RISC-V Vector

RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Compliance test).

Nuclei AI Library Optimized For RISC-V Vector

RISC-V Vectorized Bencmark Suite. based on https://github.com/RALC88/riscv-vectorized-benchmark-suite

Hair recoloring on RISC-V with OpenCV

RISCV Vector Kernel C/LLVM-IR generator

Nuclei Audio Library Optimized For RISC-V Packed-SIMD and Vector

Examples of Halide language algorithms running on RISC-V

MagicMirror² module: Departure monitor for the RVV (Regensburger Verkehrsverbund) bus system (ÖPNV, public transport)

Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings