docs: EDA landscape competitive analysis + consolidated roadmap#204
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docs: EDA landscape competitive analysis + consolidated roadmap#204anadon wants to merge 2 commits into
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Survey of circuit-design, SPICE, PCB, FPGA, and silicon tooling (free and commercial), with a JLS-centered compatibility matrix and an honest competitive assessment. Answers the stakeholder question "could JLS compete with Xilinx, Intel, TI, and TSMC" by separating the four industries those names occupy — design-capture/logic, FPGA implementation, ASIC sign-off, and silicon foundry — and showing JLS lives at the educational end of the first layer. Establishes the "on-ramp to, not competitor of" framing: JLS's VCD and structural Verilog-2005 exports are genuine standards-based bridges into the open HDL/FPGA toolchain (Icarus, Verilator, GTKWave, Surfer, Yosys, nextpnr), while ASIC/PDK/foundry rows are category boundaries, not gaps to fill. Includes an interchange-format scorecard and recommended next steps (board-aware HDL export, in-editor test panel) consistent with the existing HDL roadmap in docs/hdl-support-research.md. Facts gathered by a three-angle web-research pass, cited, with uncertainties flagged. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01C2T7YjioSrPMDZBeVA67R4
Adds docs/roadmap.md: a single ordered picture of where JLS is headed, built on the strategy in eda-landscape-competitive-analysis.md and the staged HDL work in hdl-support-research.md. Opens with the end goal (best free digital-logic teaching tool + the friendliest on-ramp from a drawn circuit to logic on real open hardware), states what the goal deliberately excludes (FPGA/ASIC suites, foundries, homegrown SPICE/PCB engines), then lays out a dependency-ordered path that maps every phase onto existing open issues: Phase 0 Correctness & foundation #33 #198 #77 #93-96 #91/#162/#159 Phase 1 Win the educational category #59 #199-202 #73 #75 #76 #86 (+board-aware export, test panel) Phase 2 Become the on-ramp/hub #61 #62 #63 (+bitstream handoff, vcd/cocotb interop) Phase 3 Extension architecture (gate) #78 #84 #77 Phase 4 Reach (parallel) collab #163/#167-171, trust #82/#134/#188/#101, web (spike) Phase 5 Frontier, gated SPICE via ngspice, PCB via KiCad netlist Proposed-but-unfiled items are marked (propose). SPICE/PCB are placed last and integration-only, gated on the extension architecture shipping plus demonstrated demand plus maintainer bandwidth, with recorded revisit triggers — consistent with the repo's scope-decision culture. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01C2T7YjioSrPMDZBeVA67R4
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What & why
Adds two related strategy documents under
docs/, in the repo's conventionfor dated, cited research/strategy reports (like
hdl-support-research.md).1.
docs/eda-landscape-competitive-analysis.md— a cited survey of thecircuit-design, SPICE, PCB, FPGA, and silicon tooling landscape (free and
commercial), with a JLS-centered compatibility matrix. It answers the
recurring "could JLS compete with Xilinx, Intel, TI, and TSMC?" question by
separating the four industries those names occupy — design capture/logic,
FPGA implementation, ASIC sign-off, and silicon foundry — and establishes the
"on-ramp to, not competitor of" framing. JLS's VCD and structural
Verilog-2005 exports are genuine standards-based bridges into the open
HDL/FPGA toolchain; ASIC/PDK/foundry rows are category boundaries, not gaps to
fill. Facts from a three-angle web-research pass, cited, with uncertainty
flags.
2.
docs/roadmap.md— a single dependency-ordered picture of where JLS isheaded, consolidating what is today scattered across tracking issues (#33,
#59, #96, #163, #188). It opens with the end goal (best free digital-logic
teaching tool + friendliest on-ramp from a drawn circuit to logic on real open
hardware), states what the goal deliberately excludes, and maps every phase
onto existing open issues:
SPICE and PCB are placed last and integration-only, gated on the extension
architecture shipping plus demonstrated demand plus maintainer bandwidth, with
recorded revisit triggers — consistent with the repo's scope-decision culture.
Items not yet filed as issues are marked (propose).
Neither document is linked from the README's normative-spec list, matching how
the other research reports under
docs/are handled.Closes #
Testing
Documentation-only change; no code or contracts are touched, so no regression
test pins it and
mvn verifybehavior is unaffected. Internal links and issuereferences were checked by hand against the current open-issue list.
🤖 Generated with Claude Code
https://claude.ai/code/session_01C2T7YjioSrPMDZBeVA67R4